Displaying 20 results from an estimated 515 matches for "tmp1".
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2009 Dec 22
2
[LLVMdev] LegalizeDAG Error?
The LegalizeDAG.cpp file has this code in SelectionDAGLegalize::PromoteNode:
case ISD::BSWAP: {
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
Results.push_back(Tmp1);
break;
}
Notice the first DAG.getNode() c...
2010 Mar 19
3
strange behavior, adds new field by non-existent field
data:
> tmp1
Date HrMn Temp Q.4
1 19450101 0900 -37.0 1
2 19450101 1000 -35.9 2
3 19450101 1100 -35.9 3
4 19450101 1200 -36.4 4
5 19450101 1300 -36.4 5
6 19450101 1400 -36.4 6
7 19450101 1500 -36.4 7
8 19450101 1600 -37.5 9
Accidentally, I did this (I meant to write Q.4 instead of Q here...
2008 Nov 11
4
[LLVMdev] Invalid comparison instruction generation
Eli,
Using the variables from the original IR,
assuming tmp == tmp1 and assume the value is not nan
ogt(tmp, tmp1) is !isnan(tmp) && !isnan(tmp1) && tmp > tmp1, or false
ule(tmp, tmp1) is isnan(tmp) || isnan(tmp1) || tmp <= tmp1, or true
So, this is invalid, or am I misunderstanding what ogt and ule stand
for?
Assuming this is valid, why con...
2009 Dec 22
0
[LLVMdev] LegalizeDAG Error?
On Dec 22, 2009, at 2:38 PMPST, Bill Wendling wrote:
> The LegalizeDAG.cpp file has this code in
> SelectionDAGLegalize::PromoteNode:
>
> case ISD::BSWAP: {
> unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
> Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
> Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
> Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
> DAG.getConstant(DiffBits,
> TLI.getShiftAmountTy()));
> Results.push_back(Tmp1);
> break;
> }
&g...
2013 Oct 04
3
[Bug 10182] New: Deleted file not shown in logfile (--log-file) unless out-format option is specified
...behavior where deleted files won't be reported in the logfile
specified with "--log-file" option unless the "--out-format" (which is related
to the *output format* as stated in the documentation) is specified.
To reproduce the bug simply run:
### no format option
mkdir tmp1 tmp2
touch tmp1/test
rsync -r --delete --log-file=transfer.log tmp1/ tmp2
cat transfer.log
# 2013/10/04 12:57:17 [20413] building file list
# 2013/10/04 12:57:17 [20413] >f+++++++++ test
# 2013/10/04 12:57:17 [20413] sent 76 bytes received 32 bytes total size 0
rm transfer.log tmp1/te...
2006 Mar 06
1
Sort problem in merge()
Hello!
I am merging two datasets and I have encountered a problem with sort.
Can someone please point me to my error. Here is the example.
## I have dataframes, first one with factor and second one with factor
## and integer
> tmp1 <- data.frame(col1 = factor(c("A", "A", "C", "C", "0", "0")))
> tmp2 <- data.frame(col1 = factor(c("C", "D", "E", "F")), col2 = 1:4)
> tmp1
col1
1 A
2 A
3 C
4 C
5 0
6...
2015 Aug 05
0
[PATCH 7/8] Add Neon intrinsics for Silk noise shape feedback loop.
...rd1_Q20, rd2_Q20;
opus_int32 exc_Q14, LPC_exc_Q14, xq_Q14, Gain_Q10;
@@ -248,21 +248,7 @@ void silk_noise_shape_quantizer(
/* Noise shape feedback */
silk_assert( ( shapingLPCOrder & 1 ) == 0 ); /* check that order is even */
- tmp2 = psLPC_Q14[ 0 ];
- tmp1 = NSQ->sAR2_Q14[ 0 ];
- NSQ->sAR2_Q14[ 0 ] = tmp2;
- n_AR_Q12 = silk_RSHIFT( shapingLPCOrder, 1 );
- n_AR_Q12 = silk_SMLAWB( n_AR_Q12, tmp2, AR_shp_Q13[ 0 ] );
- for( j = 2; j < shapingLPCOrder; j += 2 ) {
- tmp2 = NSQ->sAR2_Q14[ j - 1 ];
-...
2009 Mar 19
3
[LLVMdev] Proposal to disable some of DAG combine optimizations
Some of the optimizations that the first DAG combine performs is counter
productive for our 8-bit target. For example in:
// I dropped the types because they are irrelevant.
// Excuse me for changing the syntax...
store %tmp1, %var
%tmp2 = load %var
%tmp4 = add %tmp3, %tmp2
Since load is the only user of var and since var has just be stored to,
it assumes that %tmp1 is alive and it goes ahead and removes the load
and does:
store %tmp1, var
tmp4 = add %tmp3 , %tmp1
This is great for architectures that have more than o...
2015 Nov 21
0
[Aarch64 v2 06/18] Add Neon intrinsics for Silk noise shape feedback loop.
...rd1_Q20, rd2_Q20;
opus_int32 exc_Q14, LPC_exc_Q14, xq_Q14, Gain_Q10;
@@ -248,21 +248,7 @@ void silk_noise_shape_quantizer(
/* Noise shape feedback */
silk_assert( ( shapingLPCOrder & 1 ) == 0 ); /* check that order is even */
- tmp2 = psLPC_Q14[ 0 ];
- tmp1 = NSQ->sAR2_Q14[ 0 ];
- NSQ->sAR2_Q14[ 0 ] = tmp2;
- n_AR_Q12 = silk_RSHIFT( shapingLPCOrder, 1 );
- n_AR_Q12 = silk_SMLAWB( n_AR_Q12, tmp2, AR_shp_Q13[ 0 ] );
- for( j = 2; j < shapingLPCOrder; j += 2 ) {
- tmp2 = NSQ->sAR2_Q14[ j - 1 ];
-...
2017 Oct 30
1
An iterative function
...y){
I <- which((x-y)^2>0.5)
if (length(I)==0){
a <- 0; b <-0; c<- 0
} else {
a <- min(I)
b <- x[a]
c <- y[a]}
return(list(a=a, b=b, c=c))
}
##both m1 and m2 are matrix with 3 rows and same number of columns
f <- function(m1, m2){
n <- dim(m1)[2]
tmp1 <- f0(m1[1,], m2[1,])
S2 <- which(m1[1,] > tmp1$a)
if (length(S2) == 0){
t1 <- c(tmp1$b, 0, 0)
t2 <- c(tmp1$c, 0, 0)} else {
tmp2 <- f0(m1[2,S2], m2[2, (n-length(S2)+1):n])
S3 <- S2[which(m2[2, S2] > tmp2$a)]
if (length(S3) == 0) {
t1 <- c(tm...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...:
+ switch (TLI.getOperationAction(I->getOpcode(), I->getValueType(0))) {
+ case TargetLowering::Promote:
+ Result = PromoteVectorOp(SDValue(Result, 0)).getNode();
+ break;
+ case TargetLowering::Legal: break;
+ case TargetLowering::Custom: {
+ SDValue Tmp1 = TLI.LowerOperation(SDValue(Result, 0), DAG);
+ if (Tmp1.getNode()) {
+ // FIXME: Should the returned value be recursively checked?
+ Result = Tmp1.getNode();
+ break;
+ }
+ // FALL THROUGH
+ }
+ case TargetLowering::Expand:
+ // FIX...
2014 Mar 03
3
Re: method for communication between containers
Dear Daniel,
Thank you for your email.
According to your suggestion, I tried to use the shared memory filesystem for data exchange between the host machine and the container. The steps are as follows:
1) create an empty file in the host machine (/tmp1/file1).
2) run #chmod 777 /tmp1 and #chmod 777 /tmp1/file1.
3) expose /tmp1 to the container by configuring the container with the following XML scripts.
<filesystem type="mount" accessmode="passthrough">
<source dir="/tmp1"/>
<target di...
2009 Jun 25
2
[LLVMdev] bitwise AND selector node not commutative?
...imilar patterns, as we would expect:
defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:
$RHS))>>;
defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:
$RHS))>>;
Compiling the following three works as expected:
%tmp1 = xor i32 4294967295, %b ; %tmp2 = or i32 %a, %tmp1 -->
orn r0, r0, r1
%tmp1 = xor i32 4294967295, %b ; %tmp2 = or i32 %tmp1, %a --
> orn r0, r0, r1
%tmp = xor i32 %b, 4294967295 ; %tmp1 = and i32 %a, %tmp --
> bic r0, r0, r1
But this doesn't:
%...
2010 Sep 20
5
Sorting and subsetting
...low:
tmp <- data.frame(index = gl(2,20), foo = rnorm(40))
And further assume it is sorted by index and then by the variable foo.
tmp <- tmp[order(tmp$index, tmp$foo) , ]
Now, I want to grab the first N rows of tmp for each index. In the end, what I want is the data frame 'result'
tmp1 <- subset(tmp, index == 1)
tmp2 <- subset(tmp, index == 2)
tmp1 <- tmp1[1:5,]
tmp2 <- tmp2[1:5,]
result <- rbind(tmp1, tmp2)
Does anyone see a way to subset and subsequently bind without a loop?
Harold
[[alternative HTML version deleted]]
2008 Jun 28
1
mapping one redundant index to another redundant index
Dear R users,
I have a simple problem I cannot solve, but I sure you can help.
I have two vector, let say
> tmp1 <- c("a", "a", "b", "c")
> tmp2 <- c("a", "a", "b", "c", "c", "d")
and I want to create a matrix of two column for which I have all the
combinations of the same character, let say like this...
2009 Mar 23
3
[LLVMdev] Proposal to disable some of DAG combine optimizations
...lireza.Moshtaghi at microchip.com wrote:
> Some of the optimizations that the first DAG combine performs is
> counter
> productive for our 8-bit target. For example in:
>
> // I dropped the types because they are irrelevant.
> // Excuse me for changing the syntax...
> store %tmp1, %var
> %tmp2 = load %var
> %tmp4 = add %tmp3, %tmp2
>
> Since load is the only user of var and since var has just be stored
> to,
> it assumes that %tmp1 is alive and it goes ahead and removes the load
> and does:
>
> store %tmp1, var
> tmp4 = add %tmp3 , %tmp1
>...
2012 May 21
3
[LLVMdev] Bug in SUB expansion going back to LLVM 2.6
...LLVM 2.6 and still shows up in trunk.
case ISD::SUB: {
EVT VT = Node->getValueType(0);
assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
"Don't know how to expand this subtraction!");
Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
br...
2008 Nov 11
0
[LLVMdev] Invalid comparison instruction generation
On Mon, Nov 10, 2008 at 5:00 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Eli,
> Using the variables from the original IR,
> assuming tmp == tmp1 and assume the value is not nan
> ogt(tmp, tmp1) is !isnan(tmp) && !isnan(tmp1) && tmp > tmp1, or false
> ule(tmp, tmp1) is isnan(tmp) || isnan(tmp1) || tmp <= tmp1, or true
Correct; in fact, ogt and ule are exact opposites.
> So, this is invalid, or am I misunderst...