search for: tmp14

Displaying 20 results from an estimated 29 matches for "tmp14".

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2010 Apr 20
2
[LLVMdev] How to delete a instruction?
Hi, when I delete some instruction, I got some error prompt message. - %i.0.reg2mem.0 = phi i32 [ 0, %bb5 ], [ %indvar.next, %bb12 ] ; <i32> [#uses=2] - %s.0.reg2mem.0 = phi i32 [ 0, %bb5 ], [ %tmp16, %bb12 ] ; <i32> [#uses=1] - %tmp14 = tail call i32 @foobar(i32 %i.0.reg2mem.0) nounwind ; <i32> [#uses=1] - %tmp16 = add i32 %tmp14, %s.0.reg2mem.0 ; <i32> [#uses=2] %indvar.next = add i32 %i.0.reg2mem.0, 1 ; <i32> [#uses=2] %exitcond = icmp eq i32 %indvar.next, %n ; <i1> [#uses=1...
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
...1] %tmp10 = and i1 %tmp8, %tmp9 ; <i1> [#uses=1] %tmp11 = load i32* @src-ip ; <i32> [#uses=1] %tmp12 = and i32 %tmp11, -16777216 ; <i32> [#uses=1] %tmp13 = icmp eq i32 %tmp12, 721420288 ; <i1> [#uses=3] %tmp14 = and i1 %tmp2, %tmp5 ; <i1> [#uses=1] %tmp15 = and i1 %tmp13, %tmp14 ; <i1> [#uses=1] tail call void @spa.assert(i1 %tmp15) %tmp16 = and i1 %tmp8, %tmp10 ; <i1> [#uses=1] %tmp17 = and i1 %tmp13, %tmp16...
2008 Jan 12
1
[LLVMdev] Labels
...p slt i32 %tmp1, %tmp2 br i1 %tmp3, label %cond_next11, label %cond_true cond_true: %tmp5 = tail call i32 @yyrefill( ) %tmp6 = icmp eq i32 %tmp5, 0 br i1 %tmp6, label %UnifiedReturnBlock, label %cond_next11 cond_next11: %tmp12 = load i8** @yybuf, align 4 %tmp13 = load i32* @yypos, align 4 %tmp14 = getelementptr i8* %tmp12, i32 %tmp13 %tmp15 = load i8* %tmp14, align 1 %tmp1516 = sext i8 %tmp15 to i32 %tmp18 = icmp eq i32 %tmp1516, %c br i1 %tmp18, label %cond_true21, label %UnifiedReturnBlock cond_true21: %tmp23 = add i32 %tmp13, 1 store i32 %tmp23, i32* @yypos, align 4 ret i32 1 U...
2007 Jun 12
3
[LLVMdev] ARM backend problem ?
...%inc = alloca i32 store i32 5, i32* %n store i32 1, i32* %f store i32 1, i32* %i store i32 0 , i32* %zero store i32 1 , i32* %inc %tmp7 = load i32* %n %tmp8 = load i32* %zero %tmp6 = icmp sgt i32 %tmp7, %tmp8 br i1 %tmp6, label %then4, label %else12 then4: %tmp14 = load i32* %i %tmp16 = load i32* %n %tmp18 = load i32* %inc %tmp15 = add i32 %tmp16, %tmp18 %tmp13 = icmp slt i32 %tmp14, %tmp15 br i1 %tmp13, label %then11, label %else12 then11: %tmp20 = load i32* %f %tmp22 = alloca i32 store i32 1 , i32* %tmp22 %tmp23 = load i32*...
2013 Oct 27
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
...shl nuw nsw i32 %tmp3, 24 %tmp6 = getelementptr inbounds i8* %x_arg, i64 2 %tmp7 = load i8* %tmp6, align 1 %tmp8 = zext i8 %tmp7 to i32 %tmp9 = shl nuw nsw i32 %tmp8, 16 %tmp10 = or i32 %tmp9, %tmp4 %tmp12 = getelementptr inbounds i8* %x_arg, i64 1 %tmp13 = load i8* %tmp12, align 1 %tmp14 = zext i8 %tmp13 to i32 %tmp15 = shl nuw nsw i32 %tmp14, 8 %tmp16 = or i32 %tmp10, %tmp15 %tmp19 = load i8* %x_arg, align 4 %tmp20 = zext i8 %tmp19 to i32 %tmp21 = or i32 %tmp16, %tmp20 ret i32 %tmp21 } attributes #0 = { nounwind readonly } --- Is there a reason why this can't be...
2009 Jan 06
2
[LLVMdev] LLVM Optmizer
...ndvar.next, %bb3 ], [ 0, %entry ] ; <i32> [#uses=3] %2 = add i32 %indvar, 2 ; <i32> [#uses=1] %3 = icmp sgt i32 %2, %paraml ; <i1> [#uses=1] %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] br i1 %3, label %bb5.loopexit, label %bb3 bb5.loopexit: ; preds = %bb3 %tmp14 = add i32 %parami, 1 ; <i32> [#uses=1] %tmp15 = mul i32 %indvar, %tmp14 ; <i32> [#uses=1] %varx.111 = add i32 %tmp15, %varx.110 ; <i32> [#uses=1] %4 = add i32 %varx.111, %parami ; <i32> [#uses=1] %phitmp = add i32 %4, 1 ; <i32> [#uses=1] br label %bb5 bb5:...
2010 Apr 20
0
[LLVMdev] How to delete a instruction?
...ructions to delete with an Undef value first and then delete the instruction. -- John T. > > - %i.0.reg2mem.0 = phi i32 [ 0, %bb5 ], [ %indvar.next, %bb12 ] ; > <i32> [#uses=2] > - %s.0.reg2mem.0 = phi i32 [ 0, %bb5 ], [ %tmp16, %bb12 ] ; <i32> > [#uses=1] > - %tmp14 = tail call i32 @foobar(i32 %i.0.reg2mem.0) nounwind ; <i32> > [#uses=1] > - %tmp16 = add i32 %tmp14, %s.0.reg2mem.0 ; <i32> [#uses=2] > %indvar.next = add i32 %i.0.reg2mem.0, 1 ; <i32> [#uses=2] > %exitcond = icmp eq i32 %indvar.next, %n...
2007 Jun 12
0
[LLVMdev] ARM backend problem ?
...i32* %i > > store i32 0 , i32* %zero > > store i32 1 , i32* %inc > > > > %tmp7 = load i32* %n > > %tmp8 = load i32* %zero > > %tmp6 = icmp sgt i32 %tmp7, %tmp8 > > br i1 %tmp6, label %then4, label %else12 > > > > then4: > > %tmp14 = load i32* %i > > %tmp16 = load i32* %n > > %tmp18 = load i32* %inc > > %tmp15 = add i32 %tmp16, %tmp18 > > %tmp13 = icmp slt i32 %tmp14, %tmp15 > > br i1 %tmp13, label %then11, label %else12 > > > > then11: > > %tmp20 = load i32* %f >...
2010 Nov 23
1
[LLVMdev] Unrolling loops into constant-time expressions
...%tmp18 = mul i33 %tmp15, %tmp17 %tmp8 = mul i32 %tmp4, %tmp6 %tmp19 = lshr i33 %tmp18, 1 %2 = shl i32 %tmp8, 2 %tmp20 = trunc i33 %tmp19 to i32 %tmp12 = mul i32 %x, 5 %tmp1125 = and i32 %2, -8 %tmp21 = mul i32 %tmp20, 1431655764 %tmp13 = add i32 %tmp1125, %tmp12 %tmp14 = add i32 %tmp13, -4 %tmp22 = sub i32 %tmp14, %tmp21 ret i32 %tmp22 ; <label>:3 ; preds = %0 ret i32 0 } which has no loop, which means that clang -O3 is capable of: * unrolling expressions like for(int i = 0; i < n; i++) r...
2015 Jun 11
4
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
...r inbounds [1024 x float], [1024 x float]* > @x, i64 0, i64 %tmp9 > %tmp11 = load float, float* %tmp10, align 8, !tbaa !2 > %tmp12 = getelementptr inbounds [1024 x float], [1024 x float]* > @y, i64 0, i64 %tmp8 > %tmp13 = load float, float* %tmp12, align 4, !tbaa !2 > %tmp14 = fadd float %tmp11, %tmp13 > store float %tmp14, float* %tmp10, align 8, !tbaa !2 > %tmp15 = add nsw i64 %k.01, 2 > %exitcond.1 = icmp eq i64 %tmp15, 512 > br i1 %exitcond.1, label %bb1, label %bb2 > } > > !0 = !{i32 1, !"PIC Level", i32 2} > !1 =...
2015 Jun 10
3
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
I am testing vectorization on the following test case: float x[1024], y[1024]; void myloop1() { for (long int k = 0; k < 512; k++) { x[2*k] = x[2*k]+y[k]; } } Vectorization failed due to "unsafe dependent memory operation". I traced the LoopAccessAnalysis.cpp and found the reason is the NoWrapFlag for SCEVAddRecExpr is not set and consequently the
2013 Oct 28
0
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
...getelementptr inbounds i8* %x_arg, i64 2 > %tmp7 = load i8* %tmp6, align 1 > %tmp8 = zext i8 %tmp7 to i32 > %tmp9 = shl nuw nsw i32 %tmp8, 16 > %tmp10 = or i32 %tmp9, %tmp4 > %tmp12 = getelementptr inbounds i8* %x_arg, i64 1 > %tmp13 = load i8* %tmp12, align 1 > %tmp14 = zext i8 %tmp13 to i32 > %tmp15 = shl nuw nsw i32 %tmp14, 8 > %tmp16 = or i32 %tmp10, %tmp15 > %tmp19 = load i8* %x_arg, align 4 > %tmp20 = zext i8 %tmp19 to i32 > %tmp21 = or i32 %tmp16, %tmp20 > ret i32 %tmp21 > } > > attributes #0 = { nounwind readonly } &...
2009 Jun 24
0
[LLVMdev] LLVM frontend supporting arbitrary bit-width integral datatypes
Hi Adam, > One problem, I was trying to solve was, that I need to declare variables of let's say 5-bit width like 'i5 var', > the maximal bit-width may be limited to 64 bits. I need such variables to represent instruction's operands, > example is at the end this message. any standard compliant C compiler supports i5, believe it or not. Try this: #include
2010 Nov 07
0
[LLVMdev] Hoisting elements of array argument into registers
...2]* %sp, i64 0, i64 3 store i32 0, i32* %3, align 4 %4 = icmp eq i32 %a, 0 br i1 %4, label %wf.exit, label %bb.nph.i bb.nph.i: ; preds = %entry %.promoted1.i = load i32* %1, align 4 %tmp12.i = add i32 %a, -1 %tmp13.i = zext i32 %tmp12.i to i33 %tmp14.i = add i32 %a, -2 %tmp15.i = zext i32 %tmp14.i to i33 %tmp16.i = mul i33 %tmp13.i, %tmp15.i %tmp17.i = lshr i33 %tmp16.i, 1 %tmp18.i = trunc i33 %tmp17.i to i32 %tmp20.i = mul i32 %.promoted1.i, 5 %tmp21.i = add i32 %tmp20.i, -5 %tmp22.i = mul i32 %tmp21.i, %tmp12.i %tmp9.i = mul i...
2009 Jun 24
3
[LLVMdev] Replacing instruction in LLVM IR by an intrinsics
Hi everyone, I am trying to write a pass, that finds some instructions and replaces them with my intrinsics, but I am having problem understanding, how this should be done. Let's say I have this instruction: %tmp14 = load i32* getelementptr ([32 x i32]* @gpregs, i32 0, i64 28) and i need to read the load's operands and replace it by let's say: %tmp14 = call i32 @llvm.regread_i32.i32(i32 0, i32 1) Here is what I have: //for each instruction of a function for (inst_iterator I = inst_begin(F)...
2007 Jan 29
2
[LLVMdev] A question about GetElementPtr common subexpression elimination/loop invariant code motion
...#uses=1] %tmp6 = load int* %tmp5 ; <int> [#uses=1] %tmp10 = xor int %k.2.4, 1 ; <int> [#uses=1] %tmp13 = getelementptr [7 x [7 x [7 x int]]]* %mat, int 0, int %i.0.0.ph, int %j.1.2.ph, int %tmp10 ; <int*> [#uses=1] %tmp14 = load int* %tmp13 ; <int> [#uses=1] %tmp15 = xor int %tmp14, %tmp6 ; <int> [#uses=1] %tmp17 = add int %tmp15, %sum.0.4 ; <int> [#uses=4] %tmp19 = add int %k.2.4, 1 ; <int> [#uses=2] %tmp13 = s...
2008 May 08
0
[LLVMdev] Vector code
..._tmp10 = new GetElementPtrInst(ptr_x, const_int32_13, "tmp10", label_entry); LoadInst* float_tmp11 = new LoadInst(ptr_tmp10, "tmp11", false, label_entry); GetElementPtrInst* ptr_tmp13 = new GetElementPtrInst(ptr_y, const_int32_13, "tmp13", label_entry); LoadInst* float_tmp14 = new LoadInst(ptr_tmp13, "tmp14", false, label_entry); BinaryOperator* float_tmp15 = BinaryOperator::create(Instruction::Add, float_tmp11, float_tmp14, "tmp15", label_entry); ... So it just processes one element at a time instead of with one (SIMD) operation. Thank you, -Nic...
2008 Mar 04
0
[LLVMdev] Deleting Instructions after Intrinsic Creation
...ouble> [#uses=1] %tmp45.i = fptosi double %tmp4.i1 to i32 ; <i32> [#uses=1] %tmp9.i = fdiv double %tmp3.i, 1.000000e+02 ; <double> [#uses=1] %tmp910.i = fptosi double %tmp9.i to i32 ; <i32> [#uses=1] %tmp14.i = fdiv double %tmp3.i, 4.000000e+02 ; <double> [#uses=1] %tmp1415.i = fptosi double %tmp14.i to i32 ; <i32> [#uses=1] %tmp18.i = add i32 %tmp45.i, %tmp5.i ; <i32> [#uses=1] %tmp20.i = sub i32 %tmp18.i, %tmp910.i...
2008 Mar 04
1
[LLVMdev] Deleting Instructions after Intrinsic Creation
...lt;double> [#uses=1] %tmp45.i = fptosi double %tmp4.i1 to i32 ; <i32> [#uses=1] %tmp9.i = fdiv double %tmp3.i, 1.000000e+02 ; <double> [#uses=1] %tmp910.i = fptosi double %tmp9.i to i32 ; <i32> [#uses=1] %tmp14.i = fdiv double %tmp3.i, 4.000000e+02 ; <double> [#uses=1] %tmp1415.i = fptosi double %tmp14.i to i32 ; <i32> [#uses=1] %tmp18.i = add i32 %tmp45.i, %tmp5.i ; <i32> [#uses=1] %tmp20.i = sub i32 %tmp18.i, %tmp910.i...
2008 May 08
2
[LLVMdev] Vector code
...const_int32_13, > "tmp10", label_entry); > LoadInst* float_tmp11 = new LoadInst(ptr_tmp10, "tmp11", false, > label_entry); > GetElementPtrInst* ptr_tmp13 = new GetElementPtrInst(ptr_y, > const_int32_13, > "tmp13", label_entry); > LoadInst* float_tmp14 = new LoadInst(ptr_tmp13, "tmp14", false, > label_entry); > BinaryOperator* float_tmp15 = BinaryOperator::create(Instruction::Add, > float_tmp11, float_tmp14, "tmp15", label_entry); > ... > > So it just processes one element at a time instead of with one (SIMD)...