search for: tmp12

Displaying 20 results from an estimated 39 matches for "tmp12".

Did you mean: tmp1
2011 Oct 06
2
[LLVMdev] A potential bug
...// eliminated ... 5. %tmp49 = load i64* %0, align 8 // eliminated ... 6. store i64 %tmp49, i64* %1, align 8 // eliminated ... 7. %2 = bitcast %struct.timeval* %end to i64* // eliminated ... 8. %3 = bitcast %struct.timeval* %agg.tmp12 to i64* // eliminated ... 9. %tmp50 = load i64* %2, align 8 // eliminated ... 10. store i64 %tmp50, i64* %3, align 8 // eliminated ... 11. %tv_sec = getelementptr inbounds %struct.timeval* %agg.tmp, i32 0, i32 0 12. %tv_sec.safe_r = call...
2011 Oct 06
2
[LLVMdev] A potential bug
...%0, align 8                             // eliminated >> ... >> 6.  store i64 %tmp49, i64* %1, align 8                         // eliminated >> ... >> 7.  %2 = bitcast %struct.timeval* %end to i64*             // eliminated ... >> 8.  %3 = bitcast %struct.timeval* %agg.tmp12 to i64*   // eliminated ... >> 9.  %tmp50 = load i64* %2, align 8                               // >> eliminated ... >> 10.  store i64 %tmp50, i64* %3, align 8                           // >> eliminated ... >> 11.  %tv_sec = getelementptr inbounds %struct.timeval* %agg...
2011 Oct 06
0
[LLVMdev] A potential bug
...%tmp49 = load i64* %0, align 8                             // eliminated > ... > 6.  store i64 %tmp49, i64* %1, align 8                         // eliminated > ... > 7.  %2 = bitcast %struct.timeval* %end to i64*             // eliminated ... > 8.  %3 = bitcast %struct.timeval* %agg.tmp12 to i64*   // eliminated ... > 9.  %tmp50 = load i64* %2, align 8                               // > eliminated ... > 10.  store i64 %tmp50, i64* %3, align 8                           // > eliminated ... > 11.  %tv_sec = getelementptr inbounds %struct.timeval* %agg.tmp, i32 0, i32 &gt...
2011 Oct 06
0
[LLVMdev] A potential bug
...// > eliminated > >> ... > >> 6. store i64 %tmp49, i64* %1, align 8 // > eliminated > >> ... > >> 7. %2 = bitcast %struct.timeval* %end to i64* // eliminated > ... > >> 8. %3 = bitcast %struct.timeval* %agg.tmp12 to i64* // eliminated ... > >> 9. %tmp50 = load i64* %2, align 8 // > >> eliminated ... > >> 10. store i64 %tmp50, i64* %3, align 8 // > >> eliminated ... > >> 11. %tv_sec = getelementptr inbou...
2011 Oct 06
1
[LLVMdev] A potential bug
...gt; >> 6.  store i64 %tmp49, i64* %1, align 8                         // >> >> eliminated >> >> ... >> >> 7.  %2 = bitcast %struct.timeval* %end to i64*             // >> >> eliminated ... >> >> 8.  %3 = bitcast %struct.timeval* %agg.tmp12 to i64*   // eliminated >> >> ... >> >> 9.  %tmp50 = load i64* %2, align 8                               // >> >> eliminated ... >> >> 10.  store i64 %tmp50, i64* %3, align 8                           // >> >> eliminated ... >> >&...
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
...=1] %tmp8 = icmp eq i32 %tmp3, 168296448 ; <i1> [#uses=2] %tmp9 = icmp ne i32 %tmp6, 168296704 ; <i1> [#uses=1] %tmp10 = and i1 %tmp8, %tmp9 ; <i1> [#uses=1] %tmp11 = load i32* @src-ip ; <i32> [#uses=1] %tmp12 = and i32 %tmp11, -16777216 ; <i32> [#uses=1] %tmp13 = icmp eq i32 %tmp12, 721420288 ; <i1> [#uses=3] %tmp14 = and i1 %tmp2, %tmp5 ; <i1> [#uses=1] %tmp15 = and i1 %tmp13, %tmp14 ; <i1> [#uses=1] tail call voi...
2013 Oct 27
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
...x_arg, i64 3 %tmp2 = load i8* %tmp1, align 1 %tmp3 = zext i8 %tmp2 to i32 %tmp4 = shl nuw nsw i32 %tmp3, 24 %tmp6 = getelementptr inbounds i8* %x_arg, i64 2 %tmp7 = load i8* %tmp6, align 1 %tmp8 = zext i8 %tmp7 to i32 %tmp9 = shl nuw nsw i32 %tmp8, 16 %tmp10 = or i32 %tmp9, %tmp4 %tmp12 = getelementptr inbounds i8* %x_arg, i64 1 %tmp13 = load i8* %tmp12, align 1 %tmp14 = zext i8 %tmp13 to i32 %tmp15 = shl nuw nsw i32 %tmp14, 8 %tmp16 = or i32 %tmp10, %tmp15 %tmp19 = load i8* %x_arg, align 4 %tmp20 = zext i8 %tmp19 to i32 %tmp21 = or i32 %tmp16, %tmp20 ret i32 %tmp2...
2010 Nov 23
1
[LLVMdev] Unrolling loops into constant-time expressions
...p7 = zext i32 %tmp6 to i33 %tmp5 = zext i32 %tmp4 to i33 %tmp17 = zext i32 %tmp16 to i33 %tmp15 = mul i33 %tmp5, %tmp7 %tmp18 = mul i33 %tmp15, %tmp17 %tmp8 = mul i32 %tmp4, %tmp6 %tmp19 = lshr i33 %tmp18, 1 %2 = shl i32 %tmp8, 2 %tmp20 = trunc i33 %tmp19 to i32 %tmp12 = mul i32 %x, 5 %tmp1125 = and i32 %2, -8 %tmp21 = mul i32 %tmp20, 1431655764 %tmp13 = add i32 %tmp1125, %tmp12 %tmp14 = add i32 %tmp13, -4 %tmp22 = sub i32 %tmp14, %tmp21 ret i32 %tmp22 ; <label>:3 ; preds = %0 ret i32 0 } wh...
2015 Jun 11
4
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
...6 > store float %tmp7, float* %tmp3, align 16, !tbaa !2 > %tmp8 = or i64 %k.01, 1 > %tmp9 = shl nsw i64 %tmp8, 1 > %tmp10 = getelementptr inbounds [1024 x float], [1024 x float]* > @x, i64 0, i64 %tmp9 > %tmp11 = load float, float* %tmp10, align 8, !tbaa !2 > %tmp12 = getelementptr inbounds [1024 x float], [1024 x float]* > @y, i64 0, i64 %tmp8 > %tmp13 = load float, float* %tmp12, align 4, !tbaa !2 > %tmp14 = fadd float %tmp11, %tmp13 > store float %tmp14, float* %tmp10, align 8, !tbaa !2 > %tmp15 = add nsw i64 %k.01, 2 > %exi...
2015 Jun 10
3
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
I am testing vectorization on the following test case: float x[1024], y[1024]; void myloop1() { for (long int k = 0; k < 512; k++) { x[2*k] = x[2*k]+y[k]; } } Vectorization failed due to "unsafe dependent memory operation". I traced the LoopAccessAnalysis.cpp and found the reason is the NoWrapFlag for SCEVAddRecExpr is not set and consequently the
2010 Nov 07
0
[LLVMdev] Hoisting elements of array argument into registers
...tore i32 0, i32* %2, align 4 %3 = getelementptr inbounds [4 x i32]* %sp, i64 0, i64 3 store i32 0, i32* %3, align 4 %4 = icmp eq i32 %a, 0 br i1 %4, label %wf.exit, label %bb.nph.i bb.nph.i: ; preds = %entry %.promoted1.i = load i32* %1, align 4 %tmp12.i = add i32 %a, -1 %tmp13.i = zext i32 %tmp12.i to i33 %tmp14.i = add i32 %a, -2 %tmp15.i = zext i32 %tmp14.i to i33 %tmp16.i = mul i33 %tmp13.i, %tmp15.i %tmp17.i = lshr i33 %tmp16.i, 1 %tmp18.i = trunc i33 %tmp17.i to i32 %tmp20.i = mul i32 %.promoted1.i, 5 %tmp21.i = add i32 %tmp...
2008 Jan 12
1
[LLVMdev] Labels
...d i32* @yypos, align 4 %tmp2 = load i32* @yylimit, align 4 %tmp3 = icmp slt i32 %tmp1, %tmp2 br i1 %tmp3, label %cond_next11, label %cond_true cond_true: %tmp5 = tail call i32 @yyrefill( ) %tmp6 = icmp eq i32 %tmp5, 0 br i1 %tmp6, label %UnifiedReturnBlock, label %cond_next11 cond_next11: %tmp12 = load i32* @yypos, align 4 %tmp13 = add i32 %tmp12, 1 store i32 %tmp13, i32* @yypos, align 4 ret i32 1 UnifiedReturnBlock: ret i32 0 } define i32 @yymatchChar(i32 %c) { entry: %tmp1 = load i32* @yypos, align 4 %tmp2 = load i32* @yylimit, align 4 %tmp3 = icmp slt i32 %tmp1, %tmp2 br i1 %t...
2006 Mar 06
1
Sort problem in merge()
...ot;0", "0"))) > tmp2 <- data.frame(col1 = factor(c("C", "D", "E", "F")), col2 = 1:4) > tmp1 col1 1 A 2 A 3 C 4 C 5 0 6 0 > tmp2 col1 col2 1 C 1 2 D 2 3 E 3 4 F 4 ## Now merge them > (tmp12 <- merge(tmp1, tmp2, by.x = "col1", by.y = "col1", all.x = TRUE, sort = FALSE)) col1 col2 1 C 1 2 C 1 3 A NA 4 A NA 5 0 NA 6 0 NA ## As you can see, sort was applied, since row order is not the same as ## in tmp1. Reading h...
2010 Nov 06
2
[LLVMdev] Hoisting elements of array argument into registers
I am seeing the wf loop get optimized just fine with llvm 2.8 (and almost as good with head). I'm running on Mac OS X 10.6. I have an apple supplied llvm-gcc and a self compiled llvm 2.8. When I run $ llvm-gcc -emit-llvm -S M.c $ opt -O2 M.s | llvm-dis I see that: 1. Tail recursion has been eliminated from wf 2. The accesses to sp have been promoted to registers 3. The loop has
2008 Aug 13
1
[LLVMdev] Alloca Outside of Entry Block
This is the right answer for C's alloca. The question probably referred to LLVM IR's alloca, however. On Aug 13, 2008, at 11:07 AMPDT, Mike Stump wrote: > On Aug 13, 2008, at 10:49 AM, John Criswell wrote: >> Is it legal to have an alloca in a basic block other than a >> function's entry block? > > How else could you generate code for: > > #include
2011 Dec 09
1
[LLVMdev] Branch Instruction layout
Given an instruction like this: br i1 %tmp12, label %bb5, label %bb6 I'm confused as to why Operand(1) = bb6 and not bb5 and why Operand(2) is bb5 and not bb6. Why in the instruction does the true path always list first but when accessing the operands of the instruction, it is backwards? Is there a particular reason for this? ----------...
2013 Oct 28
0
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
...lign 1 > %tmp3 = zext i8 %tmp2 to i32 > %tmp4 = shl nuw nsw i32 %tmp3, 24 > %tmp6 = getelementptr inbounds i8* %x_arg, i64 2 > %tmp7 = load i8* %tmp6, align 1 > %tmp8 = zext i8 %tmp7 to i32 > %tmp9 = shl nuw nsw i32 %tmp8, 16 > %tmp10 = or i32 %tmp9, %tmp4 > %tmp12 = getelementptr inbounds i8* %x_arg, i64 1 > %tmp13 = load i8* %tmp12, align 1 > %tmp14 = zext i8 %tmp13 to i32 > %tmp15 = shl nuw nsw i32 %tmp14, 8 > %tmp16 = or i32 %tmp10, %tmp15 > %tmp19 = load i8* %x_arg, align 4 > %tmp20 = zext i8 %tmp19 to i32 > %tmp21 = or...
2008 Dec 01
2
[LLVMdev] Question in LLVM IR
...ppear in any of the register names? int foo(int a, int b) { int x=0,y=0; if(a+b>10){ x=b-a; y=i-2*b; }else{ x=2*a+b; y=b-2*i; } return(x+y); } translates to %tmp11 = add i32 %a.0, %b.0 %tmp12 = icmp sgt i32 %tmp11, 10 br i1 %tmp12, label %bb15, label %bb32 bb15: ; preds = %entry %tmp29.pn38 = shl i32 %b.0, 1 %tmp18 = sub i32 %i, %a.0 %y.039 = add i32 %tmp18, %b.0 %tmp3540 = sub i32 %y.039, %tmp29.pn...
2007 Aug 03
1
[LLVMdev] Adding intrinsic with variable argument list HOWTO.
...tomop( i8* getelementptr ([7 x i8]* @.str, i32 0, i32 0), i32 %tmp78 ) tail call void (i8*, ...)* @llvm.tce.customop( i8* getelementptr ([7 x i8]* @.str, i32 0, i32 0), i32 10 ) tail call void (i8*, ...)* @llvm.tce.customop( i8* getelementptr ([7 x i8]* @.str, i32 0, i32 0), i32 %tmp12 ) declare void @llvm.tce.customop(i8*, ...) No I need to add code to llvm/lib/Target/TCE/TCEInstrInfo.td, for recognizing that variable argument intrinsic and I have no idea how it's done. Right now I'm trying following: def CustomOpParams : SDTypeProfile<0,2,[]>; def customop...
2008 Jul 24
2
[LLVMdev] Indirect Branch Representation
...; preds = %L2 ptrtoint i8* inttoptr (i32 1 to i8*) to i32 br label %bb10* *bb9: ; preds = %L2 ptrtoint i8* inttoptr (i32 2 to i8*) to i32 br label %bb10 bb10: ; preds = %bb9, %bb %x.0 = phi i32 [ 2, %bb9 ], [ 1, %bb ] %tmp12 = add i32 %x.0, 10 br label %return return: ret i32 %tmp12* ** *indirectgoto: ; No predecessors! switch i32 undef, label %L1 [ i32 1, label %L1 i32 2, label %L2 ] }* *declare i32 @puts(i8*)* *declare i32 @atoi(i8*) * ** T...