search for: tmds

Absence of a TMDS Info Table is common on Optimus setups where the NVIDIA gpu is not connected directly to any outputs. Reporting an error in this scenario is too harsh. Accordingly, change the error message to an info message. By default the error message also causes a boot flicker for these sytems. Signed-off-b...

...ate(struct drm_connector *connector, struct dcb_output *dcbe, > case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; > case DCB_OUTPUT_DP: > nv_encoder->dp.no_interlace = caps->sor[or].dp.no_interlace; > + type = DRM_MODE_ENCODER_TMDS; > + break; > case DCB_OUTPUT_TMDS: > + nv_encoder->tmds.max_mhz = caps->sor[or].tmds.max_mhz; > + type = DRM_MODE_ENCODER_TMDS; > + break; > default: > type = DRM_MODE_ENCODER_TMDS; &...

...file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 3e72876..7681b01 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -936,7 +936,8 @@ static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, tmdstableptr = ROM16(bios->data[bitentry->offset]); if (!tmdstableptr) { - NV_ERROR(drm, "Pointer to TMDS table invalid\n"); + /* Happens on NVD7 and other Optimus cards with no outputs */ + NV_INFO(drm, "TMDS tabl...

..._create(struct drm_connector *connector, struct dcb_output *dcbe, > case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; > case DCB_OUTPUT_DP: > nv_encoder->dp.no_interlace = caps->dp[or].no_interlace; > + type = DRM_MODE_ENCODER_TMDS; > + break; > case DCB_OUTPUT_TMDS: > + nv_encoder->tmds.max_mhz = caps->tmds[or].max_mhz; > + type = DRM_MODE_ENCODER_TMDS; > + break; > default: > type = DRM_MODE_ENCODER_TMDS; >...

On 11/04/2015 08:41 AM, Ilia Mirkin wrote: > From: Hauke Mehrtens <hauke at hauke-m.de> > > Without this patch a pixel clock rate above 165 MHz on a TMDS link is > assumed to be dual link. This is true for DVI, but not for HDMI. HDMI > supports no dual link, but it supports pixel clock rates above 165 MHz. > Only activate Dual Link mode when it is actual possible. > > Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> > Sig...

From: Hauke Mehrtens <hauke at hauke-m.de> Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actual possible. Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> Signed-off-by: Ilia Mirkin <im...

On Tue, Nov 3, 2015 at 7:02 PM, Ben Skeggs <skeggsb at gmail.com> wrote: > On 11/04/2015 08:41 AM, Ilia Mirkin wrote: >> From: Hauke Mehrtens <hauke at hauke-m.de> >> >> Without this patch a pixel clock rate above 165 MHz on a TMDS link is >> assumed to be dual link. This is true for DVI, but not for HDMI. HDMI >> supports no dual link, but it supports pixel clock rates above 165 MHz. >> Only activate Dual Link mode when it is actual possible. >> >> Signed-off-by: Hauke Mehrtens <hauke at hauk...

From: Hauke Mehrtens <hauke at hauke-m.de> Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actually possible and requested. Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> [imirkin: check f...

From: Hauke Mehrtens <hauke at hauke-m.de> Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actually possible and requested. Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> [imirkin: check f...

...onnector *connector, struct dcb_output *dcbe, >> case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; >> case DCB_OUTPUT_DP: >> nv_encoder->dp.no_interlace = caps->sor[or].dp.no_interlace; >> + type = DRM_MODE_ENCODER_TMDS; >> + break; >> case DCB_OUTPUT_TMDS: >> + nv_encoder->tmds.max_mhz = caps->sor[or].tmds.max_mhz; >> + type = DRM_MODE_ENCODER_TMDS; >> + break; >> default: >> typ...

...rm/nouveau/dispnv50/disp.c @@ -1433,7 +1433,12 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe, case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; case DCB_OUTPUT_DP: nv_encoder->dp.no_interlace = caps->dp[or].no_interlace; + type = DRM_MODE_ENCODER_TMDS; + break; case DCB_OUTPUT_TMDS: + nv_encoder->tmds.max_mhz = caps->tmds[or].max_mhz; + type = DRM_MODE_ENCODER_TMDS; + break; default: type = DRM_MODE_ENCODER_TMDS; break; diff --git a/drm/nouveau/nouveau_connector.c b/drm/nouveau/nouveau_connector.c index 074e6d52..a955f225 100...

...ouveau/dispnv50/disp.c @@ -1433,7 +1433,12 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe, case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; case DCB_OUTPUT_DP: nv_encoder->dp.no_interlace = caps->sor[or].dp.no_interlace; + type = DRM_MODE_ENCODER_TMDS; + break; case DCB_OUTPUT_TMDS: + nv_encoder->tmds.max_mhz = caps->sor[or].tmds.max_mhz; + type = DRM_MODE_ENCODER_TMDS; + break; default: type = DRM_MODE_ENCODER_TMDS; break; diff --git a/drm/nouveau/nouveau_connector.c b/drm/nouveau/nouveau_connector.c index 074e6d52..65fac604...

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...how to use the X.Org automatic submission script after realizing that I had to change the script in order for OpenChrome DDX to build in the first place. OpenChrome DDX Version 0.6 has added the following new features. - First official support for CX700, VX700, and VX800 chipsets integrated TMDS transmitter (i.e., DVI support) - Initial support for Silicon Image SiI 164 TMDS transmitter OpenChrome DDX Version 0.6 has the following improvements. - Improved FP reinitialization when resuming from standby (HP 2133 Mini-Note, FIC CE260 / CE261 based netbooks like Everex CloudBook and S...

...ery well. I've seen dongles > > that automagically change the DFP type from DP++ to DP/HDMI depending > > on what's plugged in, and I've also seen dongles that leave the DFP > > type to DP++. > > Well, our internal logic certainly knows if it's driving DP or TMDS. I > just don't remember how it knows this. You'll be driving DP in this case. The DFP will be the one driving DP or TMDS depending on what's plugged in. -- Ville Syrjälä Intel

small update to my last version I sent out. Patches 3-6 are optional and should only improve detecting the max clocks for HDMI and DP, but they didn't underwent big testing and I am a bit concerned, that it might break detecting the DP limits on some boards. Karol Herbst (6): kms/nv50: move nv50_mstm out of the dp union in nouveau_encoder kms/nv50: reject interlaced modes if the hardware

This is mainly for dropping interlaced modes on DP connectors if the GPU would otherwise display garbage or EVO timesout. It also adds experimental detection of the HDMI clock limit we currently hard limit depending on the GPU generation. Starting with GF110 GPUs, we can retrieve the limit directly from the GPU and may make the hdmimhz parameter obsolete. Testing this series with 2560x1440 or

...nouveau 0000:01:00.0: Attempting to load BIOS image from PRAMIN [ 0.219181] [drm] nouveau 0000:01:00.0: ... appears to be valid [ 0.219184] [drm] nouveau 0000:01:00.0: BIT BIOS found [ 0.219187] [drm] nouveau 0000:01:00.0: Bios version 60.86.34.00 [ 0.219191] [drm] nouveau 0000:01:00.0: TMDS table revision 2.0 not currently supported [ 0.219194] [drm] nouveau 0000:01:00.0: Found Display Configuration Block version 4.0 [ 0.219196] [drm] nouveau 0000:01:00.0: Raw DCB entry 0: 02000300 00000028 [ 0.219199] [drm] nouveau 0000:01:00.0: Raw DCB entry 1: 01000302 00100030 [ 0.2192...

...out, such as 12/16bpc, YUV420, etc. I've verified that with this code, a GP108 (GT1030) can switch between 4k at 60 and 1920x1080 at 60 on a LG 4K TV. Further, I've verified via i2c tools, that the SCDC writes really do happen. I suspect that the patch for keeping track of the high-speed TMDS setting is somehow off, esp if one were to switch between HDMI and DVI on the same port, or DP and HDMI. I'm quite confused about OR's vs HEAD's, and how to tell whether a register is indexed by one or the other. But at least it works a little bit! Note that I have limited testing equi...

...y: 2097152 kiB > [ 3.919110] [TTM] Initializing pool allocator > [ 3.919120] [TTM] Initializing DMA pool allocator > [ 3.919141] nouveau 0000:01:00.0: DRM: VRAM: 256 MiB > [ 3.919146] nouveau 0000:01:00.0: DRM: GART: 1048576 MiB > [ 3.919152] nouveau 0000:01:00.0: DRM: TMDS table version 2.0 > [ 3.919157] nouveau 0000:01:00.0: DRM: DCB version 4.0 > [ 3.919162] nouveau 0000:01:00.0: DRM: DCB outp 00: 04000310 00000028 > [ 3.919167] nouveau 0000:01:00.0: DRM: DCB outp 01: 02011300 00000028 > [ 3.919171] nouveau 0000:01:00.0: DRM: DCB outp 02: 01...