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On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: > Hi, > > On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>> Hi, >>> >>>> (4) llc -march=hexagon test.ll -o test.s >>>> >>>> '' is not a recognized processor for this target (ignoring processor) >>>> 0...

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > however, is that...

On Tue, Nov 1, 2011 at 11:44 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hello all, > > We would like to contribute a new backend for Qualcomm's Hexagon > processor.  We will actively maintain the port once it is accepted. > Hexagon is a VLIW core that is used principally in modem and low power > audio applications in...

Hi, On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > On 7/3/2012 5:01 AM, Duncan Sands wrote: >> Hi, >> >>> (4) llc -march=hexagon test.ll -o test.s >>> >>> '' is not a recognized processor for this target (ignoring processor) >>> 0 llc 0x08c2512b >>>...

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

Hi Sebastian, On 19/07/12 05:57, Sebastian Pop wrote: > On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: >> Hi, >> >> On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >>> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>>> Hi, >>>> >>>>> (4) llc -march=hexagon test.ll -o test.s >>>>> >>>>> '' is not a recognized processor for this target (ignoring process...

On 7/3/2012 5:01 AM, Duncan Sands wrote: > Hi, > >> (4) llc -march=hexagon test.ll -o test.s >> >> '' is not a recognized processor for this target (ignoring processor) >> 0 llc 0x08c2512b >> Stack dump: >> 0. Program arguments: llc -march=hexagon test.ll -o test.s >> 1. Running pass 'Function Pass Manager' on module

Hello all, We would like to contribute a new backend for Qualcomm's Hexagon processor. We will actively maintain the port once it is accepted. Hexagon is a VLIW core that is used principally in modem and low power audio applications in Qualcomm's chip sets. We have a patch for both llvm and for clang. As this is a new port, these patches are quite large (approximately 26k and 3k

Hi Eli, On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> Hey folks, >> >> We are having some difficulty with how we have been representing our >> predicate registers, and wanted some advice from the list.  First, we >> had been representing our predicate registers as 1 bit (i1).  The truth, &g...

It would probably also help to add some systems added to the buildbot master to test on your actual hardware. deep On Tue, Nov 1, 2011 at 7:32 PM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Thanks, Eric and Eli.  We will do that, and will add some tests to > include with our submission. > > We are also in the process of getting our simulator and C library (both > proprietary) released under a new license so that folks can download > the...

Currently the only two targets that disable CFI are Hexagon and powerpc targeting BGP. Is that still correct? The current integrated assembler is working for PPC, no? For Hexagon, it has been disabled since the initial checkin. There is still no support for cfi? Thanks, Rafael

Thanks, Eric and Eli. We will do that, and will add some tests to include with our submission. We are also in the process of getting our simulator and C library (both proprietary) released under a new license so that folks can download them and actually run programs. That's a couple of months away, though, and doesn't really help much for creating LLVM regression tests. Still, it

...From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Tuesday, November 01, 2011 1:58 PM To: Tony Linthicum Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Contributing new backend to LLVM On Tue, Nov 1, 2011 at 11:44 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hello all, > > We would like to contribute a new backend for Qualcomm's Hexagon > processor.  We will actively maintain the port once it is accepted. > Hexagon is a VLIW core that is used principally in modem and low power > audio applications in...

Hi Sebastian, On 22/05/2012 23:25, Sebastian Pop wrote: > Hi Eli, > > On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman<eli.friedman at gmail.com> wrote: >> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum<tlinth at codeaurora.org> wrote: >>> Hey folks, >>> >>> We are having some difficulty with how we have been representing our >>> predicate registers, and wanted some advice from the list. First, we >>> had been representing our predicate registers as 1 bit...

On 11/1/2011 3:46 PM, Chris Lattner wrote: > > If relevant, I'd suggest splitting it up as: > > 1. Changes to LLVM code outside your target directory. > 2. Your new target directory. > 3. Clang patches. > > As others have pointed out, you really do need some basic regression tests to make sure that the backend is working. Also, make sure to update this: >

My apologies. Shouldn't it just be removed since it is now in a subdirectory? On 12/15/2011 11:38 PM, Marc J. Driftmeyer wrote: > File: trunk/llvm/lib/Target/Hexagon/CMakeLists.txt > > set(LLVM_TARGET_DEFINITIONS Hexagon.td) > > tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) > tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) > tablegen(LLVM

On 12/12/2011 4:49 PM, Eric Christopher wrote: > > On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: > >> >> On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: >> >>> On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: >>>> >>>> On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: >>>> >>>>> Hi folks,

On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: > > On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: > >> Hi folks, >> >> I just committed a new backend for the Hexagon processor. After >> committing, I was able to successfully check out, build and test with >> the new changes. The x86_64 build on the buildbot is failing, >> however.

Hi folks, I just committed a new backend for the Hexagon processor. After committing, I was able to successfully check out, build and test with the new changes. The x86_64 build on the buildbot is failing, however. Here's the build error: llvm[2]: Linking Debug+Asserts executable llvm-mc /home/baldrick/osuosl/slave/llvm-x86_64/llvm/tools/llvm-mc/Debug+Asserts/llvm-mc.o: In function