search for: tilera

No. The gcc cross compiler being used (tilera-gcc) is indeed 64-bit. Thanks On Tue, Oct 28, 2014 at 11:01 AM, Anton Korobeynikov < anton at korobeynikov.info> wrote: > Looks like your gcc is 32-bit and you're trying to load 64-bit plugin. > > On Tue, Oct 28, 2014 at 8:27 PM, Ajay Panyala <ajay.panyala at gmail.com>...

Hi Brian, Thanks for sharing your experience with dragonegg. I would like to use tilera-gcc as the compiler driver. native gcc would not be able to handle things like tilera specific intrinsics in the source code. I built dragonegg using GCC=/path/to/tilera-gcc48/bin/tile-gcc LLVM_CONFIG=/path/to/tilera-llvm/bin/tilegx-llvm-config make and also tried only emitting the IR /path/...

I am using a gcc (v 4.8.2) cross compiler for the tilera architecture. There is an LLVM (v 3.3) cross compiler available for tilera ( http://tilera.github.io/llvm), but the frontend only has partial support for certain tilera intrinsics and no OpenMP support. Hence, I have decided to use DragonEgg (v 3.3) to resolve this. I was able to build DragonEgg,...

Hi, On behalf of Tilera Corporation, I'd like to contribute llvm ports to Tilera's TILE-Gx architecture and wish this could be submitted to main llvm tree. TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More informati...

On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: > Hi all, > > Updated the patches for TILE-Gx backend: > > 1. added initial regression tests for tilegx codegen. > 2. added initial regression tests for MC Layer. > 3. fixed those commenting style issues. > > please review, thanks. This is a huge patch, an...

On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: > On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >> Hi all, >> >> Updated the patches for TILE-Gx backend: >> >> 1. added initial regression tests for tilegx codegen. >> 2. added initial regression tests for MC Layer. >> 3. fixed those commenting style issues. >> >> please revie...

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Thursday, February 28, 2013 6:09:20 PM > Subject: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor > > Hi, > > On behalf of Tilera Co...

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Friday, March 1, 2013 1:34:15 AM > Subject: Re: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core p...

Hello, I would like to know if the ARM architecture is well supported. At Xen.org it is mentionned in available architectures, but does it work really well ? I''m looking at CPU like "Tile64" from Tilera : http://www.tilera.com/products/processors/TILE64 The wiki http://wiki.xensource.com/xenwiki/XenARM doesn''t seem to be up to date. Is it ? Any advice ? Thanks, Olivier _______________________________________________ Xen-arm mailing list Xen-arm@lists.xensource.com http://lists.xenso...

Hi, I would like to inform the community that I'm releasing the backend for tile64 I developed in the past several months. It can be downloaded from http://pnyf.inf.elte.hu/juhda/projects/tilera/ The version for LLVM 3.1 is a minimalist functioning implementation. Now I am working on utilizing the VLIW packetizer of LLVM, and other improvements are planned for the future. I would be pleased to answer your comments and questions about the backend both via this mailing list or in private m...

...Regards, Jiong > > -Hal > >> TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address >> space, >> and 64-bit instructions. TILE-Gx has load-store architecture ISAs. >> >> More information on the architectures is available at >> http://www.tilera.com/scm/docs/index.html. >> >> the attached patches contains the following main features for tilegx >> backend: >> >> 1. general function. >> 2. PIC/TLS/JumpTable. >> 3. Instructoin Bundling for VLIW. >> 4. Basic support for Asm Parser. >> 5. MC...

...Jiong >> >> -Hal >> >> TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address >> space, >> and 64-bit instructions. TILE-Gx has load-store architecture ISAs. >> >> More information on the architectures is available at >> http://www.tilera.com/scm/docs/index.html . >> >> the attached patches contains the following main features for tilegx >> backend: >> >> 1. general function. >> 2. PIC/TLS/JumpTable. >> 3. Instructoin Bundling for VLIW. >> 4. Basic support for Asm Parser. >> 5. M...

...ller's stack reserve slot 0 > > Comments should start with a capital letter and end with a full stop. Hi Damitri, thanks for your time to review, I will fix these things according to llvm coding style doc. --- Regards, Jiong > > Dmitri > -- Regards, Jiong. Wang Tilera Corporation.

...ggestions on how could this target get included in LLVM mainline. === Backend Intro === TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More information on the architectures is available at http://www.tilera.com/scm/docs/index.html. features supported --- 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Asm Parser (no support for bundle syntax .s, need modification on generic MC code to support this) 5. MC Layer (support instruction bundle), MCJIT support. regression re...

On Wed, Sep 05, 2012 at 07:48:48PM +0200, JUHASZ David wrote: > Hi, > > I would like to inform the community that I'm releasing the backend for > tile64 I developed in the past several months. It can be downloaded from > > http://pnyf.inf.elte.hu/juhda/projects/tilera/ > > The version for LLVM 3.1 is a minimalist functioning implementation. Now > I am working on utilizing the VLIW packetizer of LLVM, and other > improvements are planned for the future. > > I would be pleased to answer your comments and questions about the > backend both vi...

On Mar 8, 2013, at 2:31 AM, Jiong Wang <jiwang at tilera.com> wrote: > On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: >> On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >>> Hi all, >>> >>> Updated the patches for TILE-Gx backend: >>> >>> 1. added initial regression...

On Fri, Mar 1, 2013 at 4:52 PM, Jiong Wang <jiwang at tilera.com> wrote: > On 03/01/2013 10:42 PM, Hal Finkel wrote: >> >> >> As some of the llvm modules are in active development, for example MC >> Layer, we want to return code to community repository first, so that >> it will be easy to keep pace with llvm main tree. &gt...

Hi ML readers, I am PhD student and I probably would have access to some many-core platforms for my experiments. Then I would like to know if someone is working on a backend for these platforms and in particular for the Tilera TilePro 64? Best, Julien.

On Fri, Mar 08, 2013 at 12:33:58AM +0800, Jiong Wang wrote: > please review, thanks. configure.ac: I guess it would be preferable to not enable it by default for the moment. include/llvm/Support/FEnv.h: What is supposed to handle? Build on/for Tile? Does the platform provide fenv.h but in a broken way? lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp: Is this change intentional? Personally, I

...of them are about float precision issue) 于 2013/3/16 2:37, Tom Stellard 写道: > On Fri, Mar 15, 2013 at 05:38:28PM +0800, Jiong Wang wrote: >> Hi Chandler, >> >> on 2013/3/15 17:15, Chandler Carruth wrote: >>> On Fri, Mar 15, 2013 at 1:54 AM, Jiong Wang <jiwang at tilera.com >>> <mailto:jiwang at tilera.com>> wrote: >>> >>> I agree that everyone should contribute to keep the community >>> active and vigorious. But I think there are difference between >>> contributors. >>> >>>...