search for: tilegx

...t, for example MC Layer, we want to return code to community repository first, so that it will be easy to keep pace with llvm main tree. > > Will you be able to setup a buildbot on this architecture? If so, can it be connected to the public system? yes, I guess it's OK to setup a tilegx buildbot with connection to public system. I will confirm this with the company. > > On the patch itself: > > 1. There are still a few places where there is commented-out code or #if 0 blocks; these should be removed (or replaced with real comments as appropriate). thanks, I w...

...From: "Jiong Wang" <jiwang at tilera.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Friday, March 1, 2013 1:34:15 AM > Subject: Re: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor > > > On 03/01/2013 02:57 PM, Hal Finkel wrote: > Hi Hal, > > thanks for feedback. > > > Jiong, I am happy to see the Tile backend being offered for upstream > inclusion. Among other things, in the long run, this...

On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: > Hi all, > > Updated the patches for TILE-Gx backend: > > 1. added initial regression tests for tilegx codegen. > 2. added initial regression tests for MC Layer. > 3. fixed those commenting style issues. > > please review, thanks. This is a huge patch, and reviewing it in tar.gz is hard. To facilitate review process, you can upload this to phabricator. Dmitri -- main(i,j){for(i=2;;i...

Hi all, Updated the patches for TILE-Gx backend: 1. added initial regression tests for tilegx codegen. 2. added initial regression tests for MC Layer. 3. fixed those commenting style issues. please review, thanks. I have tried to understand the new backend requirement for LLVM from the mailiing list archive, it's sure TILE-Gx backend will be actively maintained & improved, it'...

...ote: > On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: >> On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >>> Hi all, >>> >>> Updated the patches for TILE-Gx backend: >>> >>> 1. added initial regression tests for tilegx codegen. >>> 2. added initial regression tests for MC Layer. >>> 3. fixed those commenting style issues. >>> >>> please review, thanks. >> This is a huge patch, and reviewing it in tar.gz is hard. To >> facilitate review process, you can upload this...

...-Gx is a VLIW architecture with 64-bit registers, 64-bit address space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More information on the architectures is available at http://www.tilera.com/scm/docs/index.html. the attached patches contains the following main features for tilegx backend: 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Basic support for Asm Parser. 5. MC Layer (aware of VLIW), MCJIT support. I've run the regression test and standalone test-suite natively on TILE-Gx silicon. The test results are: regression --- Expected...

On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: > On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >> Hi all, >> >> Updated the patches for TILE-Gx backend: >> >> 1. added initial regression tests for tilegx codegen. >> 2. added initial regression tests for MC Layer. >> 3. fixed those commenting style issues. >> >> please review, thanks. > This is a huge patch, and reviewing it in tar.gz is hard. To > facilitate review process, you can upload this to phabricator. OK,...

...ches into small chunks that can be easily reviewed. Keep in > mind that the compiler needs to work after each pass goes in. :-) Just like with AArch64, this is not a reasonable requirement for a new backend. The tarball contains essentially three different parts: (1) Generic changes to recogniz TileGX as triple etc. (2) The target subdirectory. (3) The clang logic for va_arg etc. While (1) can be and should be split off, it doesn't change match in terms of patch size, since the majority will stay in item (2). Joerg

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Thursday, February 28, 2013 6:09:20 PM > Subject: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor > > Hi, > > On behalf of Tilera Corporation, I'd like to contribute llvm ports to > Tilera's TILE-Gx > architecture and wish this could be submitted to main llvm tree. Jiong, I am happy to see the Tile backend being of...

On 03/02/2013 04:50 AM, Dmitri Gribenko wrote: > You also need tests for Clang bits, too. > > Mechanical issues: > > +/// getTileRegisterNumbering - Given the enum value for some register, > +/// return the number that it corresponds to. > > Please don't duplicate function and class name in comments. Existing > code does this, but current style guidelines advise not

...return code to community repository first, so that > it will be easy to keep pace with llvm main tree. > I think this makes sense; but my impression is that the community will want a clear idea that this will be maintained and improved for the foreseeable future. Hi Hal, sure, tilegx will be actively maintained & improved. >> >> >> 2. There are no regression tests -- using the test-suite is obviously >> useful, but targeted regression tests are essential. yes, regression >> tests will be added later. > I don't speak for everybody, but I&...

On Fri, Mar 08, 2013 at 12:33:58AM +0800, Jiong Wang wrote: > please review, thanks. configure.ac: I guess it would be preferable to not enable it by default for the moment. include/llvm/Support/FEnv.h: What is supposed to handle? Build on/for Tile? Does the platform provide fenv.h but in a broken way? lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp: Is this change intentional? Personally, I

...source code and some further information is available at > > http://aesop.ece.umd.edu > > The main components of the released implementation are loop memory dependence analysis and parallel code generation using calls to POSIX threads. Interesting ! I happen to finish the initial TileGX backend support, which is a many core processor. I am looking forward to testing AESOP on TileGX silicon. --- Regards, Jiong > Since we currently have only a 2-person development team, we are still on LLVM 3.0, and some of the code could use some cleanup. Still, we hope that the work will be...

...so that >> it will be easy to keep pace with llvm main tree. >> I think this makes sense; but my impression is that the community will >> want a clear idea that this will be maintained and improved for the >> foreseeable future. > > Hi Hal, > > sure, tilegx will be actively maintained & improved. > >>> >>> >>> 2. There are no regression tests -- using the test-suite is obviously >>> useful, but targeted regression tests are essential. yes, regression >>> tests will be added later. >> >> I...

...er. Regression Result === Expected Passes : 13363 Expected Failures : 84 Unsupported Tests : 76 Unexpected Failures: 21 20 of the unexpected failures are caused by lack of old jit support. Test-Suite Result === Expected Passes : 953 Unexpected Failures: 14 (all 14 failures has the same output as tilegx gcc, most of them are about float precision issue) 于 2013/3/16 2:37, Tom Stellard 写道: > On Fri, Mar 15, 2013 at 05:38:28PM +0800, Jiong Wang wrote: >> Hi Chandler, >> >> on 2013/3/15 17:15, Chandler Carruth wrote: >>> On Fri, Mar 15, 2013 at 1:54 AM, Jiong Wang <...

Hi, We would like to inform the community that we're releasing a version of our research compiler, "AESOP", developed at UMD using LLVM. AESOP is a distance-vector-based autoparallelizing compiler for shared-memory machines. The source code and some further information is available at http://aesop.ece.umd.edu The main components of the released implementation are loop memory

...Expected Failures : 84 > Unsupported Tests : 76 > Unexpected Failures: 21 > > 20 of the unexpected failures are caused by lack of old jit support. > > Test-Suite Result > === > Expected Passes : 953 > Unexpected Failures: 14 > (all 14 failures has the same output as tilegx gcc, > most of them are about float precision issue) > > > > 于 2013/3/16 2:37, Tom Stellard 写道: >> On Fri, Mar 15, 2013 at 05:38:28PM +0800, Jiong Wang wrote: >>> Hi Chandler, >>> >>> on 2013/3/15 17:15, Chandler Carruth wrote: >>>> On...

...ported Tests : 76 >> Unexpected Failures: 21 >> >> 20 of the unexpected failures are caused by lack of old jit support. >> >> Test-Suite Result >> === >> Expected Passes : 953 >> Unexpected Failures: 14 >> (all 14 failures has the same output as tilegx gcc, >> most of them are about float precision issue) >> >> >> >> 于 2013/3/16 2:37, Tom Stellard 写道: >>> On Fri, Mar 15, 2013 at 05:38:28PM +0800, Jiong Wang wrote: >>>> Hi Chandler, >>>> >>>> on 2013/3/15 17:15, Chandler Ca...

...oon (probably before > the end of march). For the moment, you should use the VMKit2 > repository as it's probably the most advanced one. Hi Gael, does it mean vmkit will based on the latest llvm after the merge finished? I run into the same issue Chris meet when trying to verify tilegx backend by compiling vmkit. JavaJIT.cpp:1262:23: error: no member named 'removeFnAttr' in 'llvm::Function' llvmFunction->removeFnAttr( then I change to vmkit2, but found it's based on 3.2 only, failed compile with latest llvm > > See you, > Gaël...

...for sharing your experience with dragonegg. I would like to use tilera-gcc as the compiler driver. native gcc would not be able to handle things like tilera specific intrinsics in the source code. I built dragonegg using GCC=/path/to/tilera-gcc48/bin/tile-gcc LLVM_CONFIG=/path/to/tilera-llvm/bin/tilegx-llvm-config make and also tried only emitting the IR /path/to/tilera-gcc48/bin/tile-gcc -fplugin=/path/to/dragonegg.so -fplugin-arg-dragonegg-emit-ir -S -o hello.ll hello.c (and still get the error: cannot load plugin dragonegg.so: wrong ELF class: ELFCLASS64 ) - Ajay On Mon, Oct 27, 2014 a...