search for: tile_flag

Displaying 20 results from an estimated 102 matches for "tile_flag".

Did you mean: tile_flags
2014 Sep 26
0
[RFC PATCH 6/7] drm/nouveau: Support marking buffers for explicit sync
...o.c b/drm/nouveau_bo.c index 534734a..68b7bdd 100644 --- a/drm/nouveau_bo.c +++ b/drm/nouveau_bo.c @@ -180,7 +180,7 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, int nouveau_bo_new(struct drm_device *dev, int size, int align, - uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, + uint32_t flags, uint32_t tile_mode, uint32_t bo_flags, struct sg_table *sg, struct nouveau_bo **pnvbo) { @@ -211,7 +211,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, INIT_LIST_HEAD(&nvbo->entry); INIT_LIST_HEAD(&nvbo->vma_list); n...
2015 Jun 15
4
[PATCH v2 0/2] drm/nouveau: option for staging ioctls and new GEM_SET_TILING ioctl
Second version of this patchset addressing Ben's comments and fixing a few extra things. This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to
2024 May 09
0
[PATCH v4] drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations
....c > index db8cbf615..186add400 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -241,28 +241,28 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, > int *align, u32 domain, > } > > nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); > - if (!nouveau_cli_uvmm(cli) || internal) { > - /* for BO noVM allocs, don't assign kinds */ > - if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { > - nvbo->kind = (tile_fl...
2024 May 08
0
[PATCH v3] drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations
....c > index db8cbf615..583c962ef 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -241,28 +241,29 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, > int *align, u32 domain, > } > > nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); > - if (!nouveau_cli_uvmm(cli) || internal) { > - /* for BO noVM allocs, don't assign kinds */ > - if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { > - nvbo->kind = (tile_fl...
2015 Jun 15
2
[PATCH v2 2/2] drm/nouveau: add GEM_SET_TILING staging ioctl
...> +void > +nouveau_bo_update_tiling(struct nouveau_drm *drm, struct nouveau_bo *nvbo, > + struct nvkm_mem *mem) > +{ > + switch (drm->device.info.family) { > + case NV_DEVICE_INFO_V0_TESLA: > + if (drm->device.info.chipset != 0x50) > + mem->memtype = (nvbo->tile_flags & 0x7f00) >> 8; > + break; > + case NV_DEVICE_INFO_V0_FERMI: > + case NV_DEVICE_INFO_V0_KEPLER: > + mem->memtype = (nvbo->tile_flags & 0xff00) >> 8; > + break; > + default: > + break; > + } > +} > + > int > nouveau_bo_new(struct d...
2014 Sep 19
2
[PATCH 0/2] nv50, nvc0: fix weirdo zs formats and their blits
There were reports of issues with gallium-nine. It's unclear whether mesa/st uses these, the patches did not produce any piglit changes. However they seem right... Ilia Mirkin (2): nv50,nvc0: add missing depth/stencil formats to tile flag selection nv50,nvc0: fix 3d blit logic for odd depth/stencil formats src/gallium/drivers/nouveau/nv50/nv50_blit.h | 21 ++++++++++++++-------
2019 Sep 10
1
[Intel-gfx] [PATCH v6 08/17] drm/ttm: use gem vma_node
.....7d5ede756711 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -186,8 +186,8 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, } struct nouveau_bo * -nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32 flags, u32 tile_mode, - u32 tile_flags) +nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags, + u32 tile_mode, u32 tile_flags) { struct nouveau_drm *drm = cli->drm; struct nouveau_bo *nvbo; @@ -195,8 +195,8 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32 flags, u32 tile_mode, struct nvif_vm...
2009 Dec 11
2
[PATCH 1/2] exa: Pre-G80 tiling support.
...4; @@ -398,15 +399,22 @@ nouveau_exa_create_pixmap(ScreenPtr pScreen, int width, int height, int depth, else if (height > 4) tile_mode = 1; else tile_mode = 0; - if (usage_hint == NOUVEAU_CREATE_PIXMAP_ZETA) + if (usage_hint & NOUVEAU_CREATE_PIXMAP_ZETA) tile_flags = 0x2800; else tile_flags = 0x7000; height = NOUVEAU_ALIGN(height, 1 << (tile_mode + 2)); - } + } else { + if (usage_hint & NOUVEAU_CREATE_PIXMAP_TILED) { + int pitch_align = + pNv->NVArch >= 0x40 ? 512 : 256; - *new_pitch = width * cpp; + *new_pitch...
2015 Jun 15
2
[PATCH v2 2/2] drm/nouveau: add GEM_SET_TILING staging ioctl
...> +void > +nouveau_bo_update_tiling(struct nouveau_drm *drm, struct nouveau_bo *nvbo, > + struct nvkm_mem *mem) > +{ > + switch (drm->device.info.family) { > + case NV_DEVICE_INFO_V0_TESLA: > + if (drm->device.info.chipset != 0x50) > + mem->memtype = (nvbo->tile_flags & 0x7f00) >> 8; > + break; > + case NV_DEVICE_INFO_V0_FERMI: > + case NV_DEVICE_INFO_V0_KEPLER: > + mem->memtype = (nvbo->tile_flags & 0xff00) >> 8; > + break; > + default: > + break; > + } > +} > + > int > nouveau_bo_new(struct...
2011 Dec 07
0
[PATCH] dri2: fix allocation of Z16 depth attachments
...ccel_common.c b/src/nv_accel_common.c index 3219dbe..51cc66a 100644 --- a/src/nv_accel_common.c +++ b/src/nv_accel_common.c @@ -71,7 +71,7 @@ nouveau_allocate_surface(ScrnInfoPtr scrn, int width, int height, int bpp, tile_mode = 0x00; if (usage_hint & NOUVEAU_CREATE_PIXMAP_ZETA) - tile_flags = 0x1100; /* S8Z24 */ + tile_flags = (bpp == 16) ? 0x0100 : 0x1100; /* Z16 : Z24S8 */ else tile_flags = 0xfe00; @@ -90,7 +90,7 @@ nouveau_allocate_surface(ScrnInfoPtr scrn, int width, int height, int bpp, tile_mode = 0; if (usage_hint & NOUVEAU_CREATE_PIXMAP_ZETA) -...
2015 May 20
3
[PATCH 0/2] drm/nouveau: option for staging ioctls and new SET_TILING ioctl
This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to specify the tiling options of a PRIME-imported buffer. The staging parameter will allow us
2015 Jan 02
2
[PATCH v2] nv50: enable texture compression
...5,7 @@ nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz) static uint32_t nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) { - const unsigned ms = mt->ms_x + mt->ms_y; - + const unsigned ms = util_logbase2(mt->base.base.nr_samples); uint32_t tile_flags; if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR)) @@ -96,6 +95,26 @@ nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) tile_flags = 0x60 + ms; break; default: + switch (mt->base.base.format) { + case PIPE_FORMAT_R1...
2019 Aug 21
2
[Intel-gfx] [PATCH v6 08/17] drm/ttm: use gem vma_node
On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote: > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann <kraxel at redhat.com> wrote: > > > > Hi, > > > > > > Changing the order doesn't look hard. Patch attached (untested, have no > > > > test hardware). But maybe I missed some detail ... > > > > > > I came up with
2009 Jul 10
1
Can't build xf86-video-nouveau
...no member named ?tile_mode? nouveau_exa.c: In function ?nouveau_exa_mph_broken_should_die?: nouveau_exa.c:441: warning: implicit declaration of function ?nouveau_bo_new_tile? nouveau_exa.c: In function ?nouveau_exa_pixmap_is_tiled?: nouveau_exa.c:475: error: ?struct nouveau_bo? has no member named ?tile_flags? nouveau_exa.c: In function ?nouveau_exa_pixmap_map?: nouveau_exa.c:493: error: ?struct nouveau_bo? has no member named ?tile_flags? nouveau_exa.c: In function ?nouveau_exa_pixmap_unmap?: nouveau_exa.c:521: error: ?struct nouveau_bo? has no member named ?tile_flags? make[2]: *** [nouveau_exa.lo] E...
2015 Jan 02
2
[PATCH] nv50: enable texture compression
...5,7 @@ nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz) static uint32_t nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) { - const unsigned ms = mt->ms_x + mt->ms_y; - + const unsigned ms = util_logbase2(mt->base.base.nr_samples); uint32_t tile_flags; if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR)) @@ -96,6 +95,7 @@ nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) tile_flags = 0x60 + ms; break; default: + compressed = false; switch (util_format_get_blocksizebi...
2019 Sep 16
4
[PATCH 0/4] drm/nouveau: Miscellaneous fixes
From: Thierry Reding <treding at nvidia.com> Hi Ben, these are fixes for a couple of issues that I've been running into when testing on various Tegra boards. The first two patches fix up issues in the fix that I had sent out earlier to fix the regression introduced in drm-misc-next. The first one is critical because it avoids a BUG_ON as reported by Ilia, while the second is less
2015 Jan 02
1
[PATCH v2] nv50: enable texture compression
...ly always says true. However it should > probably be drm_version >= whatever. Oh sure, i'll add it! > >> { >> - const unsigned ms = mt->ms_x + mt->ms_y; >> - >> + const unsigned ms = util_logbase2(mt->base.base.nr_samples); >> uint32_t tile_flags; >> >> if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR)) >> @@ -96,6 +95,26 @@ nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) >> tile_flags = 0x60 + ms; >> break; >> default: >> +...
2009 Aug 19
1
[PATCH] drm/nouveau: Add a MM for mappable VRAM that isn't usable as scanout.
...ouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index eba257a..06c2d13 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -68,8 +68,11 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, nvbo->tile_mode = tile_mode; nvbo->tile_flags = tile_flags; - if (!nvbo->mappable && (flags & TTM_PL_FLAG_VRAM)) - flags |= TTM_PL_FLAG_PRIV0; + if (flags & TTM_PL_FLAG_VRAM) { + flags |= TTM_PL_FLAG_PRIV1; + if (!nvbo->mappable) + flags |= TTM_PL_FLAG_PRIV0; + } /* Some of the tile_flags have a periodic struc...
2009 Jun 10
1
Compilation error in nouveau_exa.c
...ion 'nouveau_exa_mph_broken_should_die': > nouveau_exa.c:441: warning: implicit declaration of function 'nouveau_bo_new_tile' > nouveau_exa.c: In function 'nouveau_exa_pixmap_is_tiled': > nouveau_exa.c:475: error: 'struct nouveau_bo' has no member named 'tile_flags' > nouveau_exa.c: In function 'nouveau_exa_pixmap_map': > nouveau_exa.c:493: error: 'struct nouveau_bo' has no member named 'tile_flags' > nouveau_exa.c: In function 'nouveau_exa_pixmap_unmap': > nouveau_exa.c:521: error: 'struct nouveau_bo'...
2016 Sep 18
5
[PATCH 1/2] Revert "bus: remove cpu_coherent flag"
...ool cpu_coherent; }; struct nvkm_device_quirk { diff --git a/drm/nouveau/nouveau_bo.c b/drm/nouveau/nouveau_bo.c index 528bdef..6887d0a 100644 --- a/drm/nouveau/nouveau_bo.c +++ b/drm/nouveau/nouveau_bo.c @@ -209,7 +209,8 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, nvbo->tile_flags = tile_flags; nvbo->bo.bdev = &drm->ttm.bdev; - nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; + if (!nvxx_device(&drm->device)->func->cpu_coherent) + nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; nvbo->page_shift = 12; if (drm->cl...