Displaying 10 results from an estimated 10 matches for "then1".
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2011 Jun 14
2
[LLVMdev] Avoiding Constant Folding
...; preds = %entry
%returnValue = or i1 true, false
....
br label %ifmerge
else: ; preds = %entry
br label %ifmerge
ifmerge: ; preds = %else, %then
...
%41 = icmp ne i32 %40, 15
br i1 %41, label %then1, label %else3
then1: ; preds = %ifmerge
%returnValue2 = or i1 true, %returnValue
else3: ; preds = %ifmerge
br label %ifmerge4
ifmerge4: ; preds = %else3, %then1
.......
2011 Jun 14
2
[LLVMdev] Avoiding Constant Folding
...label %ifmerge
>>
>> else: ; preds = %entry
>> br label %ifmerge
>>
>> ifmerge: ; preds = %else, %then
>> ...
>> %41 = icmp ne i32 %40, 15
>> br i1 %41, label %then1, label %else3
>>
>> then1: ; preds = %ifmerge
>> %returnValue2 = or i1 true, %returnValue
if control flow goes: "entry" -> "else" -> "ifmerge" -> "then1", then you will
try to use %retur...
2011 Jun 14
0
[LLVMdev] Avoiding Constant Folding
...r i1 true, false
> ....
> br label %ifmerge
>
> else: ; preds = %entry
> br label %ifmerge
>
> ifmerge: ; preds = %else, %then
> ...
> %41 = icmp ne i32 %40, 15
> br i1 %41, label %then1, label %else3
>
> then1: ; preds = %ifmerge
> %returnValue2 = or i1 true, %returnValue
>
> else3: ; preds = %ifmerge
> br label %ifmerge4
>
> ifmerge4: ...
2011 Jun 14
0
[LLVMdev] Avoiding Constant Folding
...;>> else: ; preds = %entry
>>> br label %ifmerge
>>>
>>> ifmerge: ; preds = %else, %then
>>> ...
>>> %41 = icmp ne i32 %40, 15
>>> br i1 %41, label %then1, label %else3
>>>
>>> then1: ; preds = %ifmerge
>>> %returnValue2 = or i1 true, %returnValue
>
> if control flow goes: "entry" -> "else" -> "ifmerge" -> "then1", then you...
2017 Jun 19
4
LLVM behavior different depending on function symbol name
Greetings,
I have a Zig implementation of ceil which is emitted into LLVM IR like this:
; Function Attrs: nobuiltin nounwind
define internal fastcc float @ceil(float) unnamed_addr #3 !dbg !644 {
Entry:
%x = alloca float, align 4
store float %0, float* %x
call void @llvm.dbg.declare(metadata float* %x, metadata !649, metadata
!494), !dbg !651
%1 = load float, float* %x, !dbg !652
%2 =
2011 Oct 19
0
[LLVMdev] Question regarding basic-block placement optimization
...code. =]
% cat ifchain.ll
; RUN: opt < %s -analyze -block-freq | FileCheck %s
declare void @error(i32 %i, i32 %a, i32 %b)
define i32 @test(i32 %i, i32* %a, i32 %b) {
entry:
%gep1 = getelementptr i32* %a, i32 1
%val1 = load i32* %gep1
%cond1 = icmp ugt i32 %val1, 1
br i1 %cond1, label %then1, label %else1, !prof !0
then1:
call void @error(i32 %i, i32 1, i32 %b)
br label %else1
else1:
%gep2 = getelementptr i32* %a, i32 2
%val2 = load i32* %gep2
%cond2 = icmp ugt i32 %val2, 2
br i1 %cond2, label %then2, label %else2, !prof !0
then2:
call void @error(i32 %i, i32 1, i32 %b...
2017 Jun 19
2
LLVM behavior different depending on function symbol name
...g !84
Then: ; preds = %Entry
%9 = load float, float* %x, !dbg !85
ret float %9, !dbg !87
Else: ; preds = %Entry
%10 = load i32, i32* %e, !dbg !88
%11 = icmp sge i32 %10, 0, !dbg !89
br i1 %11, label %Then1, label %Else2, !dbg !89
Then1: ; preds = %Else
%12 = load i32, i32* %e, !dbg !90
%13 = lshr i32 8388607, %12, !dbg !92
store i32 %13, i32* %m, !dbg !93
%14 = load i32, i32* %u, !dbg !94
%15 = load i32, i32* %m, !dbg !95
%16 = and i32 %14, %15,...
2011 Oct 19
3
[LLVMdev] Question regarding basic-block placement optimization
On Tue, Oct 18, 2011 at 6:58 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
>
> On Oct 18, 2011, at 5:22 PM, Chandler Carruth wrote:
>
> As for why it should be an IR pass, mostly because once the selection dag
>> runs through the code, we can never recover all of the freedom we have at
>> the IR level. To start with, splicing MBBs around requires known about
2017 Jun 19
2
LLVM behavior different depending on function symbol name
...ds = %Entry
>> %9 = load float, float* %x, !dbg !85
>> ret float %9, !dbg !87
>>
>> Else: ; preds = %Entry
>> %10 = load i32, i32* %e, !dbg !88
>> %11 = icmp sge i32 %10, 0, !dbg !89
>> br i1 %11, label %Then1, label %Else2, !dbg !89
>>
>> Then1: ; preds = %Else
>> %12 = load i32, i32* %e, !dbg !90
>> %13 = lshr i32 8388607, %12, !dbg !92
>> store i32 %13, i32* %m, !dbg !93
>> %14 = load i32, i32* %u, !dbg !94
>>...
2018 Mar 23
5
RFC: Speculative Load Hardening (a Spectre variant #1 mitigation)
...following, which test three
conditions and if all pass, loads data from memory and potentially leaks it
through some side channel:
```
# %bb.0: # %entry
pushq %rax
testl %edi, %edi
jne .LBB0_4
# %bb.1: # %then1
testl %esi, %esi
jne .LBB0_4
# %bb.2: # %then2
testl %edx, %edx
je .LBB0_3
.LBB0_4: # %exit
popq %rax
retq
.LBB0_3: # %danger
movl...