Displaying 20 results from an estimated 27 matches for "texinstruction".
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...7+
+ assert(!bindless || targ->getChipset() < NVISA_GM107_CHIPSET);
+
if (ptr) {
ptr = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(slot));
if (bindless)
@@ -2204,7 +2207,7 @@ getDestType(const ImgType type) {
}
void
-NVC0LoweringPass::convertSurfaceFormat(TexInstruction *su)
+NVC0LoweringPass::convertSurfaceFormat(TexInstruction *su, Instruction **loaded)
{
const TexInstruction::ImgFormatDesc *format = su->tex.format;
int width = format->bits[0] + format->bits[1] +
@@ -2223,21 +2226,38 @@ NVC0LoweringPass::convertSurfaceFormat(TexInstruction *su)...
2018 Sep 23
3
[Bug 108032] New: nv50_ir_lowering_gm107.cpp:326: undefined reference to `nv50_ir::NVC0LoweringPass::loadMsAdjInfo32(nv50_ir::TexInstruction::Target, unsigned int, int, nv50_ir::Value*, bool)'
...r: pedretti.fabio at gmail.com
QA Contact: nouveau at lists.freedesktop.org
CC: pendingchaos02+fdobugzilla at gmail.com
Since latest commits mesa fails to build with:
./.libs/libnouveau.a(nv50_ir_lowering_gm107.o): In function
`nv50_ir::GM107LoweringPass::handleSUQ(nv50_ir::TexInstruction*)':
/<<PKGBUILDDIR>>/build/src/gallium/drivers/nouveau/../../../../../src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp:326:
undefined reference to
`nv50_ir::NVC0LoweringPass::loadMsAdjInfo32(nv50_ir::TexInstruction::Target,
unsigned int, int, nv50_ir::Value*, bool)'...
2014 Feb 28
0
[PATCH] nv50: enable texture query lod
...odegen/nv50_ir_emit_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
index bef103f..0b0d480 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -1450,6 +1450,9 @@ CodeEmitterNV50::emitTEX(const TexInstruction *i)
code[0] = 0x01000000;
code[1] = 0x80000000;
break;
+ case OP_TXLQ:
+ code[1] = 0x60020000;
+ break;
default:
assert(i->op == OP_TEX);
break;
@@ -1790,6 +1793,7 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
case OP_TXB:
case...
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
...r_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index f010767..4a9e48f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -603,10 +603,18 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
Value *ticRel = i->getIndirectR();
Value *tscRel = i->getIndirectS();
- if (ticRel)
+ if (ticRel) {
i->setSrc(i->tex.rIndirectSrc, NULL);
- if (tscRel)
+ if (i->tex.r)
+ ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScrat...
2014 Mar 20
0
[PATCH] nvc0/ir: move sample id to second source arg to fix sampler2DMS
..._ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 3840f75..62241ba 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -666,8 +666,9 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
const int dim = i->tex.target.getDim() + i->tex.target.isCube();
const int arg = i->tex.target.getArgCount();
const int lyr = arg - (i->tex.target.isMS() ? 2 : 1);
+ const int chipset = prog->getTarget()->getChipset();
- if (prog->getTarget()->getChipse...
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 3afbf43..9ec2366 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -601,6 +601,21 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
// lod bias
// depth compare
// offsets (same as fermi, except txd which takes it with array)
+ //
+ // Maxwell (tex):
+ // array
+ // coords
+ // indirect handle
+ // sample
+ // lod bias
+ // depth compare
+ // offsets
+ //
+ // Maxwell (txd):
+ /...
2014 Apr 04
2
[PATCH 1/2] nvc0: add support for texture gather
...gen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index b716d54..a4b50ee 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -984,6 +984,9 @@ CodeEmitterGK110::emitTEX(const TexInstruction *i)
case OP_TXF:
code[1] = 0x78000000;
break;
+ case OP_TXG:
+ code[1] = 0x7dc00000;
+ break;
default:
code[1] = 0x7d800000;
break;
@@ -1005,6 +1008,11 @@ CodeEmitterGK110::emitTEX(const TexInstruction *i)
code[1]...
2017 Dec 20
2
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
...ir_lowering_gm107.cpp
index 6b9edd48645..a2427526a81 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -95,18 +95,15 @@ GM107LegalizeSSA::visit(Instruction *i)
bool
GM107LoweringPass::handleManualTXD(TexInstruction *i)
{
- static const uint8_t qOps[4][2] =
- {
- { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(MOV2, MOV2, ADD, ADD) }, // l0
- { QUADOP(SUBR, MOV2, SUBR, MOV2), QUADOP(MOV2, MOV2, ADD, ADD) }, // l1
- { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(SUBR, SUBR, MOV2, MOV2) }, // l2
-...
2014 Jul 05
1
[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved
..._ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 0e24db7..398b28f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -769,7 +769,8 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
if (dim > 2 ||
txd->tex.target.isCube() ||
arg > 4 ||
- txd->tex.target.isShadow())
+ txd->tex.target.isShadow() ||
+ txd->tex.useOffsets)
return handleManualTXD(txd);
for (int c = 0; c < dim; ++c) {
--
1.8.5.5
2014 Jul 05
0
[PATCH] nvc0: do quadops on the right texture coordinates for TXD
...wering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 8f26645..0e24db7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -712,6 +712,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
Value *zero = bld.loadImm(bld.getSSA(), 0);
int l, c;
const int dim = i->tex.target.getDim();
+ const int array = i->tex.target.isArray();
i->op = OP_TEX; // no need to clone dPdx/dPdy later
@@ -722,7 +723,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)...
2017 Dec 20
0
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
...ex 6b9edd48645..a2427526a81 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
> @@ -95,18 +95,15 @@ GM107LegalizeSSA::visit(Instruction *i)
> bool
> GM107LoweringPass::handleManualTXD(TexInstruction *i)
> {
> - static const uint8_t qOps[4][2] =
> - {
> - { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(MOV2, MOV2, ADD, ADD) }, // l0
> - { QUADOP(SUBR, MOV2, SUBR, MOV2), QUADOP(MOV2, MOV2, ADD, ADD) }, // l1
> - { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(SUBR, SUBR...
2015 Jan 04
0
[PATCH] nv50/ir: fix texture offsets in release builds
...r_lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index e283424..0d7612e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -772,7 +772,8 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
if (i->tex.useOffsets) {
for (int c = 0; c < 3; ++c) {
ImmediateValue val;
- assert(i->offset[0][c].getImmediate(val));
+ if (!i->offset[0][c].getImmediate(val))
+ assert(!"non-immediate offset");
i->tex.offset[c...
2014 Feb 19
0
[PATCH] nv50: enable cube map array texture support
...r_lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index 984a8ca..0908447 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -664,7 +664,7 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
bld.mkOp2(OP_MIN, TYPE_U32, src, src, bld.loadImm(NULL, 511));
i->setSrc(arg - 1, src);
}
- if (i->tex.target.isCube()) {
+ if (i->tex.target.isCube() && i->srcCount() > 4) {
std::vector<Value *> acube, a2d;
i...
2013 Dec 08
0
[PATCH] nv50: TXF already has integer arguments, don't try to convert from f32
...lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index caaf09f..07f3a21 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -575,14 +575,16 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
if (i->op == OP_TXB || i->op == OP_TXL)
i->swapSources(dref, lod);
- // array index must be converted to u32
if (i->tex.target.isArray()) {
- Value *layer = i->getSrc(arg - 1);
- LValue *src = new_LValue(func, FILE_GPR);
- bld.mkCvt(OP_CVT,...
2014 Feb 20
0
[PATCH] nv50: enable txg where supported
...odegen/nv50_ir_emit_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
index bef103f..e2f93bb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -1447,7 +1447,7 @@ CodeEmitterNV50::emitTEX(const TexInstruction *i)
code[0] |= 0x01000000;
break;
case OP_TXG:
- code[0] = 0x01000000;
+ code[0] |= 0x01000000;
code[1] = 0x80000000;
break;
default:
@@ -1790,6 +1790,7 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
case OP_TXB:
case OP_TXL:
case OP...
2014 Jul 05
1
[PATCH 1/2] nv50/ir: retrieve shadow compare from first arg
This can only happen with texture(samplerCubeShadow, bias), where the
compare will be in the first argument.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
2016 Mar 16
2
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
...getSrc(0)->reg.file = FILE_MEMORY_GLOBAL;
> + atom->getSrc(0)->reg.file = FILE_MEMORY_BUFFER;
> if (ptr)
> base = bld.mkOp2v(OP_ADD, TYPE_U32, base, base, ptr);
> atom->setIndirect(0, 1, NULL);
> @@ -1571,7 +1571,7 @@ NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
> *su)
> Instruction *red = bld.mkOp(OP_ATOM, su->dType, su->getDef(0));
> red->subOp = su->subOp;
> if (!gMemBase)
> - gMemBase = bld.mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, 0);
> + gMemBase = bld.mkSymbol(FILE_MEMORY_BUFFER, 0,...
2016 Mar 16
0
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
...etSrc(0)));
- atom->getSrc(0)->reg.file = FILE_MEMORY_GLOBAL;
+ atom->getSrc(0)->reg.file = FILE_MEMORY_BUFFER;
if (ptr)
base = bld.mkOp2v(OP_ADD, TYPE_U32, base, base, ptr);
atom->setIndirect(0, 1, NULL);
@@ -1571,7 +1571,7 @@ NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction *su)
Instruction *red = bld.mkOp(OP_ATOM, su->dType, su->getDef(0));
red->subOp = su->subOp;
if (!gMemBase)
- gMemBase = bld.mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, 0);
+ gMemBase = bld.mkSymbol(FILE_MEMORY_BUFFER, 0, TYPE_U32, 0);
red->s...
2016 Mar 16
0
[PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/
...= FILE_MEMORY_GLOBAL;
>> + atom->getSrc(0)->reg.file = FILE_MEMORY_BUFFER;
>> if (ptr)
>> base = bld.mkOp2v(OP_ADD, TYPE_U32, base, base, ptr);
>> atom->setIndirect(0, 1, NULL);
>> @@ -1571,7 +1571,7 @@ NVC0LoweringPass::handleSurfaceOpNVE4(TexInstruction
>> *su)
>> Instruction *red = bld.mkOp(OP_ATOM, su->dType, su->getDef(0));
>> red->subOp = su->subOp;
>> if (!gMemBase)
>> - gMemBase = bld.mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, 0);
>> + gMemBase = bld.mkSym...
2015 Nov 25
4
NV50 compute support questions
...ng ./compute there results in:
PIPE_COMPUTE_CAP_GRID_DIMENSION: { 2 }
PIPE_COMPUTE_CAP_MAX_GRID_SIZE: { 65535 65535 }
PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: { 512 512 64 }
- test_system_values
compute: codegen/nv50_ir_ra.cpp:2120: void nv50_ir::RegAlloc::InsertConstraintsPass::texConstraintNV50(nv50_ir::TexInstruction*): Assertion `tex->defExists(0) && tex->srcExists(0)' failed.
And "nbody" behaves the same as on the NVD9 card.
This is all with current mesa master.
Samual do you've a branch somewhere were the trivial/compute
example actually works ? And on what card[s] should i...