Displaying 7 results from an estimated 7 matches for "test32rr".
2015 Mar 18
6
[LLVMdev] string input for the integrated assembler
...ength instructions and a laborious hierarchy of
tblgen AsmOperands to do the job. Assembly and disassembly with
llvm-mc and llvm-objdump work fine.
As a simplification, the compiler deals almost exclusively in pseudo
instructions. By x86 analogy, using pseudos to unfold a TEST32rm into
MOV32rm + TEST32rr means I can skip the complex operand fitting effort
needed to pick specific machine instructions. There are many such
examples where handling real instructions would become a gross
overload.
One drawback of this approach is that the integrated assembler
receives only unexpanded pseudos as input,...
2014 Apr 22
2
[LLVMdev] where is F7 opcode for TEST instruction on X86?
...any hint please?
thanks.
let isCompare = 1 in {
let Defs = [EFLAGS] in {
let isCommutable = 1 in {
def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
} // isCommutable
def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
def TEST16rm : BinOpRM_F<...
2015 Mar 18
2
[LLVMdev] string input for the integrated assembler
On Tue, Mar 17, 2015 at 6:14 PM, Tim Northover <t.p.northover at gmail.com> wrote:
>> As a simplification, the compiler deals almost exclusively in pseudo
>> instructions. By x86 analogy, using pseudos to unfold a TEST32rm into
>> MOV32rm + TEST32rr means I can skip the complex operand fitting effort
>> needed to pick specific machine instructions. There are many such
>> examples where handling real instructions would become a gross
>> overload.
>>
>> One drawback of this approach is that the integrated assembler...
2007 Dec 20
1
[LLVMdev] Code Generation Problem llvm 1.9
...NOREG, -160
%EAX = MOV32rm %EBP, 1, %NOREG, -224
%EAX = ADD32ri8 %EAX, 24
%XMM0 = MOVSDrm %EBP, 1, %NOREG, -160
MOVSDmr %EBP, 1, %NOREG, -232, %XMM0
MOVSDmr %EAX, 1, %NOREG, 0, %XMM0
%EAX = CVTTSD2SIrm %ESI, 1, %NOREG, 0
%ECX = MOV32r0
TEST32rr %EAX, %EAX
JNE mbb<bb.preheader.i271,0x8c55330>
Successors according to CFG: 0x8c55330 0x8c573b0
The gdb disassembler gives me the following lines for that basic block
__exp.exit:
0xf5f6f317: movl $0xa542b70,0xffffff20(%ebp)
0xf5f6f321: mov 0xffffff20(%ebp),%eax
0xf...
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...ef> = MOVSX64rr32 %EDX<kill>; dbg:FastBoard.cpp:186:26 @[
> FastBoard.cpp:1938:21 ]
>
> .
>
> .
>
> .
>
> TEST32rr %ESI<kill>, %R8D<kill>, %EFLAGS<imp-def>; dbg:FastBoard.cpp:1940:10
>
> JNE_1 <BB#1>, %EFLAGS<imp-use,kill>; dbg:FastBoard.cpp:1940:9
>
> BB#1:
>
> %CL<def> = COPY %R9B<kill>, %ECX<imp-use,kill>, %ECX<imp-def>;
> dbg:Fas...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...>>> FastBoard.cpp:1938:21 ]
>>>
>>> .
>>>
>>> .
>>>
>>> .
>>>
>>> TEST32rr %ESI<kill>, %R8D<kill>, %EFLAGS<imp-def>;
>>> dbg:FastBoard.cpp:1940:10
>>>
>>> JNE_1 <BB#1>, %EFLAGS<imp-use,kill>; dbg:FastBoard.cpp:1940:9
>>>
>>> BB#1:
>>>
>>> %CL<def> = COPY %R9B<kill>, %E...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof,
Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts.
Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a