search for: tdrr

Dear LLVM'ers, I am browsing the instruction schedulers available in llc, and there are many: -pre-RA-sched = {default, none, simple, simple-noitin, list-burr, list-tdrr, list-td} I looked into the sources in lib/CodeGen/SelectionDAG, and I could find implementation of Sethi-Ullman numbering, list scheduling, etc. Now, I wish I could find some comparison between the schedulers. I guess you guys probably have some tests somewhere. Basically, I wish I c...

...ch modes to > balance reducing latency vs. reducing register pressure. Right. I'm actually working on implementing a variant of IPS (Goodman and Hsu, Code scheduling and register allocation in large basic blocks, http://doi.acm.org/10.1145/55364.55407) based on the existing list-td and list-tdrr schedulers; this requires handling of physical register dependencies in those schedulers, which I am currently struggling with. It's all in a very messy pre-prototype stage, but I'm getting there and will be happy to contribute my work when it's nice and clean. Thanks for the feedback,...

...bed how the variations of List Scheduling work, in -pre-RA-sched phase ? -pre-RA-sched - Instruction schedulers available (before register allocation): =source - Similar to list-burr but schedules in source order when possible =list-tdrr - Top-down register reduction list scheduling =list-burr - Bottom-up register reduction list scheduling =list-td - Top-down list scheduler =fast - Fast suboptimal l...

...rking on implementing a variant of IPS (Goodman and > Hsu, Code scheduling and register allocation in large basic blocks, > http://doi.acm.org/10.1145/55364.55407) based on the existing list-td and Well, David is a LLVM contributor himself so perhaps he can give you some pointers. > list-tdrr schedulers; this requires handling of physical register > dependencies in those schedulers, which I am currently struggling with. It's > all in a very messy pre-prototype stage, but I'm getting there and will be > happy to contribute my work when it's nice and clean. Sounds gr...

A more pressing need is a pre-regalloc scheduler that can switch modes to balance reducing latency vs. reducing register pressure. The problem is the current approach is the scheduler is locked into one mode or the other. For x86, it generally makes sense to schedule for low register pressure. That is, until you are dealing with a block that are explicitly SSE code in 64-bit mode. In that case,

...retical limits of the processor (stated to be 45.25 GFLOP/s single-precision). I've used the llc utility to test various pre-register-allocation instruction schedulers with the following results: -pre-RA-sched =default - discards ILP =list-burr - discards ILP =list-tdrr - crashes during code generation =source - preserves interleaved instruction ordering and ILP =list-hybrid - discards ILP =list-ilp - discards ILP =list-td - crashes during code generation =fast - discards ILP Can you comment? --...

Hi! I'm working on an LLVM back-end for a processor with a stack machine architecture. After experimenting with code generation directly from the LLVM representation, I'm studying the target-independant code generator. As far as I understand, there currently exists a target-independant infrastructure for legalization, instruction selection, scheduling and register allocation. It is clear

Hello, On Fri, Nov 14, 2008 at 6:57 PM, H. Johnson <misc at faradayco.com> wrote: > llc -march=x86 tempfileB.bc yields: > llc: for the -march option: : Cannot find option named 'x86'! Run llc -help and see, if any backends were linked in. It will show you list of all backends, which were 'registered' and thus known to llc. -- With best regards, Anton Korobeynikov

llc -march=x86 tempfileB.bc yields: llc: for the -march option: : Cannot find option named 'x86'! Windows build using Visual Studio 2008 Express with CMake. clang and other tools seem to also complain about the format of -march, but other command line arguments seem to be working. Tools, clang llvm-as, opt, etc., "seem" to be working. Incidently, the bytecode file was