search for: tbt

I wrote a proof of concept regarding the cpu capabilities runtime detection and choice of optimized function. I follow design which had been discussed on IRC. Also, i notice a little drawback: we must propagate the arch index through functions which don't have codec state as argument. However, if it's look good, i will continue to implement it. Best regards, -- Aur?lien Zanelli

Hi, [Sorry for the delay, I was on vacation] On Fri, Jul 17, 2020 at 01:32:10PM +0200, Karol Herbst wrote: > Filed at https://bugzilla.kernel.org/show_bug.cgi?id=208597 Thanks for reporting. I'll check your logs and try to figure if there is something we can do to make both nouveau and TBT working at the same time. > oddly enough I wasn't able to reproduce it on my XPS 9560, will ping > once something breaks.

Hi Again All, When using Asterisk with a PRI to the CO is it possible to transfer a call back out and release. In other words, once the call is connected (caller and external 3rd party) Asterisk is removed from the equation thereby freeing the PRI channels. I ask because my scenario is going to require frequent external transfers and I would like to control the PRI costs. Could this be done

...lTbS.dIr AlTbS.tXt = AlTbS.tXt aLtSb.tXt = aLtSb.tXt aLtSmBiG = aLtSmBiG aLtSmBiG.dIr = aLtSmBiG.dIr aLtSmBiG.tXt = aLtSmBiG.tXt ONESMALl = ONESMALl ONESMALL.TXt = ONESMALL.TXt oNESMALL.DIR = oNESMALL.DIR TBt.tXT = TBt.tXT TWobYTwo = TWobYTwo TWobYTwo.DIr = TWobYTwo.DIr TWobYTwo.TXt = TWobYTwo.TXt Explorer on windows-XP and windows-2000 seems to show the filenames correctly ! Also if I do a "DIR" command in a command window on windows-NT4.0 the...

On Jun 2, 2014, at 12:25 PM, Andreas Lausch / TBT wrote: > > Hi, > > thanks for the reply. > > On 2014-05-29 05:21, Charles Lepple wrote: >>> Now my questions: >>> 1. should the blazer_ser's high voltage be the voltage during charging >>> or right after I've unplugged it from the mains? >...

Hi, thanks for the reply. On 2014-05-29 05:21, Charles Lepple wrote: >> Now my questions: >> 1. should the blazer_ser's high voltage be the voltage during charging >> or right after I've unplugged it from the mains? > sounds like during charging (or more accurately, during float charging at the end of the cycle): > >

...-5.swf.trace new file mode 100644 index 0000000..1a235f1 --- /dev/null +++ b/test/trace/stage-align-5.swf.trace @@ -0,0 +1,17 @@ +Check Stage.align + +L ==> L +R ==> R +LR ==> LR +RL ==> LR +LRL ==> LR +RLR ==> LR +T ==> T +B ==> B +BT ==> TB +TB ==> TB +BTB ==> TB +TBT ==> TB +TRLB ==> LTRB +tlrb ==> LTRB +RmoviesdsdgaRsdgagaergBafsgafgaS ==> RB diff --git a/test/trace/stage-align-6.swf b/test/trace/stage-align-6.swf new file mode 100644 index 0000000..2b5fd59 Binary files /dev/null and b/test/trace/stage-align-6.swf differ diff --git a/test/trace/sta...

...stays > > limited to the particular root port leading to the NVIDIA GPU. The > > reason why I think it should to be limited is that I'm pretty certain > > the problem is not in the root port itself. I have here a KBL based > > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > > (it is connected to PCH root port) and it wakes up there just fine, so > > don't want to break that. > > > > Now, PCIe devices cannot go into D3cold all by themselves. They always > > need help from the platform side which is ACPI in this...

Hello list, we've got a PowerWalker VI 1000E/RT LCD UPS and like to use it with NUT using the blazer_ser driver. For the blazer_ser driver to display percentage, one has to add battery.voltage.high and battery.voltage.low voltages to the ups config. Here's what I received from the powerwalker customer service: Battery-Low Voltage: 21.6VDC Battery Shutdown: 19.2VDC Now my questions: 1.

...cation] > > On Fri, Jul 17, 2020 at 01:32:10PM +0200, Karol Herbst wrote: > > Filed at https://bugzilla.kernel.org/show_bug.cgi?id=208597 > > Thanks for reporting. > > I'll check your logs and try to figure if there is something we can do > to make both nouveau and TBT working at the same time. > > > oddly enough I wasn't able to reproduce it on my XPS 9560, will ping > > once something breaks. -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat

...different encoder method for operand(1) but that operand is not even propagated in Encodeinstruction.. by the way,this is how I have defined BGEID.. *def : Pat<(brcond (setcc (i32 GR32:$L), (i32 GR32:$R), SETGE), bb:$T),* * (BGEID (CMP GR32:$L, GR32:$R), bb:$T)>;* *def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset), "bgeid\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* I don't know where I am doing wrong.please provide your notes... Thanks, Mahesh B -------------- next part -------------- An HTML attachment was scrubbed......

Hi, I have added Branch condition BGEID like below… *def : Pat<(brcond (setcc (i32 GR32:$L), (i32 GR32:$R), SETGE), bb:$T),* * (BGEID (CMP GR32:$L, GR32:$R), bb:$T)>;* *def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset), "bgeid\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* *def brtarget : Operand<OtherVT>* *{* * let PrintMethod = "printPCRelImmOperand";* * let EncoderMethod = "getBranchTargetOpValue&...

On Thu, 2020-07-16 at 18:54 -0500, Bjorn Helgaas wrote: > [+cc Sasha -- stable kernel regression] > [+cc Patrick, Kai-Heng, LKML] > > On Fri, Jul 17, 2020 at 12:10:39AM +0200, Karol Herbst wrote: > > On Tue, Jul 7, 2020 at 9:30 PM Karol Herbst <kherbst at redhat.com> wrote: > > > Hi everybody, > > > > > > with the mentioned commit Nouveau

...as long as the quirk stays > limited to the particular root port leading to the NVIDIA GPU. The > reason why I think it should to be limited is that I'm pretty certain > the problem is not in the root port itself. I have here a KBL based > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > (it is connected to PCH root port) and it wakes up there just fine, so > don't want to break that. > > Now, PCIe devices cannot go into D3cold all by themselves. They always > need help from the platform side which is ACPI in this case. This is > done...

On Jun 2, 2014, at 6:48 PM, Charles Lepple wrote: > On Jun 2, 2014, at 12:25 PM, Andreas Lausch / TBT wrote: > >> >> Hi, >> >> thanks for the reply. >> >> On 2014-05-29 05:21, Charles Lepple wrote: >>>> Now my questions: >>>> 1. should the blazer_ser's high voltage be the voltage during charging >>>> or right after I...

...; limited to the particular root port leading to the NVIDIA GPU. The > > > reason why I think it should to be limited is that I'm pretty certain > > > the problem is not in the root port itself. I have here a KBL based > > > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > > > (it is connected to PCH root port) and it wakes up there just fine, so > > > don't want to break that. > > > > > > Now, PCIe devices cannot go into D3cold all by themselves. They always > > > need help from the platform s...

...against this patch, as long as the quirk stays limited to the particular root port leading to the NVIDIA GPU. The reason why I think it should to be limited is that I'm pretty certain the problem is not in the root port itself. I have here a KBL based Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold (it is connected to PCH root port) and it wakes up there just fine, so don't want to break that. Now, PCIe devices cannot go into D3cold all by themselves. They always need help from the platform side which is ACPI in this case. This is done by having the device to have...

...e particular root port leading to the NVIDIA GPU. The > > > > reason why I think it should to be limited is that I'm pretty certain > > > > the problem is not in the root port itself. I have here a KBL based > > > > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > > > > (it is connected to PCH root port) and it wakes up there just fine, so > > > > don't want to break that. > > > > > > > > Now, PCIe devices cannot go into D3cold all by themselves. They always > > > > need...

On Tue, Nov 19, 2019 at 10:50 PM Bjorn Helgaas <helgaas at kernel.org> wrote: > > [+cc Dave] > > On Thu, Oct 17, 2019 at 02:19:01PM +0200, Karol Herbst wrote: > > Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device > > states. > > > > v2: convert to pci_dev quirk > > put a proper technical explanation of the issue as a

On Fri, Jul 17, 2020 at 1:54 AM Bjorn Helgaas <helgaas at kernel.org> wrote: > > [+cc Sasha -- stable kernel regression] > [+cc Patrick, Kai-Heng, LKML] > > On Fri, Jul 17, 2020 at 12:10:39AM +0200, Karol Herbst wrote: > > On Tue, Jul 7, 2020 at 9:30 PM Karol Herbst <kherbst at redhat.com> wrote: > > > > > > Hi everybody, > > > > >