search for: targetregisterclass

Aye, I understand it's an index into an array, but what is the difference between the index i and the return value. Do I have to worry that register values from a TargetRegisterClass could be either zero based or some other base? Are there other methods that rely on zero based in the TargetRegisterClass? I thought register values were "global," but this transformation makes a register value dependent on it's TargetRegisterClass. Basically, I find it confusing to...

The method below takes in a register and returns a register. To me this makes no sense because when I already have a register, why would I need to get it? Could someone please explain the transformation that is happening here? /// getRegister - Return the specified register in the class. /// unsigned getRegister(unsigned i) const { assert(i < getNumRegs() && "Register

llvm::TargetRegisterClass::getSize() llvm::TargetRegisterClass::getAllignment() will return the size and alignment of a virtual register used both in register allocation and stack slot assignment. llvm::TargetRegisterClass::alloc_order_begin() llvm::TargetRegisterClass::alloc_order_end() will give a list of the possible p...

How do I get the TargetRegisterClass for a physical register? SSARegMap::getRegClass only works for virtual registers. -Dave

...help with me about the way to access type and size of Value. But, I want also know the interface for me to access the type or size of virtual registers in the SSA form. 1. I find no way to associate the virtual registers with the Value class. 2. I also tried to get the size of register nReg by: TargetRegisterClass::getSize(), where the TargetRegisterClass object is obtained by MachineRegisterInfo::getRegClass( nReg ). But, I found it always returned with the value 4 bytes, say, GR32 (My target is the x86-32 bits). If all virtual registers were size of 32 bits, how could we consider the alias register file...

...y LLVM IR, all of the SSA values are C++ objects derived from the Value class. For example, an Instruction object (class Instruction derives from class Value) *is* the SSA value generated by its result; they are one and the same. > 2. I also tried to get the size of register nReg by: > TargetRegisterClass::getSize(), where the TargetRegisterClass object > is obtained by MachineRegisterInfo::getRegClass( nReg ). > But, I found it always returned with the value 4 bytes, say, GR32 (My > target is the x86-32 bits). If all virtual registers were size of 32 > bits, how could we consider t...

...etPhys(VirtReg); ... assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where PhysReg may be a reserved physical register. Specificially, RegAllocPBQP::finalizeAlloc() may select a physical register thusly: const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg); PReg = RC.getRawAllocationOrder(MF).front(); ... VRM.assignVirt2Phys(LI.reg, PReg); The documentation for TargetRegisterClass::getRawAllocationOrder() notes that the collection may include reserved registers. So it seems that the PBQP allocator...

Take a look at getPhysicalRegisterRegClass( const MRegisterInfo *MRI, MVT::ValueType VT, unsigned reg) in ScheduleDAG.cpp. -- Christopher Lamb On Jun 18, 2007, at 4:52 PM, David A. Greene wrote: > How do I get the TargetRegisterClass for a physical register? > SSARegMap::getRegClass only works for virtual registers. > > -Dave > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu &g...

...e I want to insert two values, which are available in register types of FSR8RC, into a register type of FSR16RC. when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in > v4= insert_subreg implicit_def, v1, 0 the following function returns an incorrect subregclass: static const TargetRegisterClass* getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) { // Pick the register class of the subregister TargetRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1; assert(I < TRC->subregclasses_end() &&...

...able in > register > types of FSR8RC, into a register type of FSR16RC. > > when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in > >> v4= insert_subreg implicit_def, v1, 0 > > the following function returns an incorrect subregclass: > > static const TargetRegisterClass* > getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned > SubIdx) > { > // Pick the register class of the subregister > TargetRegisterInfo::regclass_iterator I = > TRC->subregclasses_begin() + SubIdx-1; > assert(I < TRC->subregclasses_end() &&amp...

On Mon, 18 Jun 2007, David Greene wrote: > So there are multiple ValueTypes here (the scalar registers each only have > one corresponding to the bit size of the register). But still, if I have > physical register MM2, that completely determines its register class. Right. > Is there some other architecture where the physical register name/number > does not completely determine its

On Tue, 19 Jun 2007, David A. Greene wrote: > The model is correct, I believe. My "yuck" comment was about the necessity > of iterating through all members of all register classes to find the classes a > physical register is in. It would be nice to have a backmap. Perhaps I'll > fiddle around with TableGen and friends and see about adding one if folks > think

On Tuesday 19 June 2007 11:20, Chris Lattner wrote: > On Tue, 19 Jun 2007, David A. Greene wrote: > > The model is correct, I believe. My "yuck" comment was about the > > necessity of iterating through all members of all register classes to > > find the classes a physical register is in. It would be nice to have a > > backmap. Perhaps I'll fiddle around

On Tuesday 19 June 2007 00:35, Chris Lattner wrote: > > Is there some other architecture where the physical register name/number > > does not completely determine its register class? > > Yes, for example, X86. On X86, we have XMM registers that can hold one of > three things: an f32 value, a f64 value, or a vector value. These are > represented by different register

...mp;              User->getOperand(2).getNode() == Node &&              User->getOperand(2).getResNo() == i) {            unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();            if (TargetRegisterInfo::isVirtualRegister(Reg)) { -            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); -            if (RegRC == RC) { +            // Allow constraining the virtual register's class within reason, +            // just like what AddRegisterOperand will allow. +            const TargetRegisterClass *ConstrainedRC +              = MRI->constra...

...], [AL, CL, DL, BL, SPL, BPL, SIL, DIL, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; class GR16_ ..... { let SubRegClassList = [GR8]; } Refer to below functions in ScheduleDAGEmit.cpp: ----------------------------------------------- static const TargetRegisterClass* getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) { // Pick the register class of the subregister TargetRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1; assert(I < TRC->subregclasses_end() && "Invalid subregis...

...reserved registers; the aliases are { 50 > 64 117 118 }). I don;t know which preg corresponds to RBP. > > You say that RBP should be saved/restored across the call. I tried to > generate that code, but, as I said in my previous mail, I don't know how > to get the appropriate TargetRegisterClass (needed to call > CreateSpillStackObject). Should I instead be generating code to save > register EBP at the start of scinstal, restoring it at the end of that > function? > > Susan > > > > ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF); >...

...= ADDrr i32, i32 *** MachineFunction at end of ISel *** # Machine code for function _Z11scalar_loopPsS_ss: IsSSA, TracksLiveness ... %31:sfgpr32 = ADDrr killed %32:sgpr32, %27:sgpr32 ... Here should not select f32 sfgpr32 register, debugger point to TargetRegisterInfo:: getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT = MVT::SimpleValueType::Any) This function has been called 10+ in LLVM, only one place give specific SVT parameter. Most of those places are hard to get the MVT::SimpleValueT...

On Monday 18 June 2007 19:02, Christopher Lamb wrote: > Take a look at getPhysicalRegisterRegClass( > const MRegisterInfo *MRI, > MVT::ValueType VT, > unsigned reg) > > in ScheduleDAG.cpp. Yuck. I was afraid of that. What is the ValueType needed for? Isn't the register id itself an indication of the ValueType it represents? Where I'm at I

...know is how to access the machine register classes. Also, I > need to know which virtual register is to be mapped into each specific > register class. I assume there is type information on the registers. I need > to know how to access it. MachineRegisterInfo::getRegClass will give you the TargetRegisterClass for a given virtual register. Each TargetRegisterClass has an "allocation order" that enumerates all physical registers valid for that class. > And a afterthought, does LLVM place casts into > different virtual registers, or do I need to include casting of floats to > integers o...