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...tried to find that in google, but I am not sure that I found what you were speaking about. Do you have a link ? I just discover that this mailing list is for speaking about LLVM developpement and usage only, so for all non LLVM related discussions, go to http://www.velocityreviews.com/forums/t964068-reflexions-about-a-new-hdl-language.html. Cheers, Jonas

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never