search for: t78

Displaying 4 results from an estimated 4 matches for "t78".

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2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...t> %t44, <3 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %t74 = fmul <4 x float> %t59, %t72 %t75 = fadd <4 x float> %t71, %t74 %t76 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2> %t78 = fmul <4 x float> %t63, %t76 %t79 = fadd <4 x float> %t75, %t78 %t80 = shufflevector <4 x float> %t50, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %t82 = fmul <4 x float> %t67, %t80 %t83 = fadd <4 x float> %t79, %t82 ret <4...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t74: ch = CopyToReg t0, Register:i64 %vreg28, t61 t62: i64 = extract_vector_elt t56, Constant:i64<5> t76: ch = CopyToReg t0, Register:i64 %vreg29, t62 t63: i64 = extract_vector_elt t56, Constant:i64<6> t78: ch = CopyToReg t0, Register:i64 %vreg30, t63 t64: i64 = extract_vector_elt t56, Constant:i64<7> t80: ch = CopyToReg t0, Register:i64 %vreg31, t64 t81: ch = TokenFactor t66, t68, t70, t72, t74, t76, t78, t80 t83: ch = CopyToReg...
2017 Feb 28
2
rL296252 Made large integer operation codegen significantly worse.
I see we're missing an isel pattern for add producing carry and doing a memory RMW. I'm going to see if adding that helps anything. ~Craig On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes. I'm seeing that as well. Not clear what's going on. > > In any case it looks to be unrelated to the alias analysis so barring
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...= callseq_start t72, TargetConstant:i64<128>, TargetConstant:i64<0> t74: i64,ch = load<LD8[FixedStack1]> t73, FrameIndex:i64<1>, undef:i64 t76: i64 = add FrameIndex:i64<1>, Constant:i64<8> t77: i64,ch = load<LD8[FixedStack1+8]> t73, t76, undef:i64 t78: i64,ch = load<LD8[FixedStack1+16]> t73, t27, undef:i64 t80: i64 = add FrameIndex:i64<1>, Constant:i64<24> t81: i64,ch = load<LD8[FixedStack1+24]> t73, t80, undef:i64 t82: i64,ch = load<LD8[FixedStack1+32]> t73, t31, undef:i64 t84: i64 = add FrameIndex:i64&...