Displaying 20 results from an estimated 178 matches for "t7".
2005 Dec 15
2
question on write.table
Hi,
I have a question on write.table:
I have a data.frame called t7 as below:
> dim(t7)
[1] 14015184 6
> t7[1:5,]
uci uce par line graphical.forms stems
1 0 0 0 0 active activ
2 0 0 0 0 policy polici
3 0 0 0 0 wc PC
4 0 0 0 0 eff elf
5 0 0 0 0...
2012 Jul 06
2
[LLVMdev] Excessive register spilling in large automatically generated functions, such as is found in FFTW
...zk_d = MULI(SUB(zk_p, zk_n));
*r2 = SUB(uk, zk);
*r0 = ADD(uk, zk);
*r3 = ADD(uk2, zk_d);
*r1 = SUB(uk2, zk_d);
}
__INLINE void L_4_4(const float *i0, const float *i1, const float *i2,
const float *i3, __m128 *r0, __m128 *r1, __m128 *r2, __m128 *r3) {
__m128 t0, t1, t2, t3, t4, t5, t6, t7;
t0 = LOAD(i0);
t1 = LOAD(i1);
t2 = LOAD(i2);
t3 = LOAD(i3);
t4 = ADD(t0, t1);
t5 = SUB(t0, t1);
t6 = ADD(t2, t3);
t7 = MULI(SUB(t2, t3));
t0 = ADD(t4, t6);
t2 = SUB(t4, t6);
t1 = SUB(t5, t7);
t3 = ADD(t5, t7);
TX2(&t0,&t1);
TX2(&t2,&t3);
*r0 = t0...
2016 Jun 22
2
LLVM Backend Issues
...!
Jeff
jeff at ubuntu:~/code$ llc -debug-only=isel dft_gf_msp.ll
=== main
Initial selection DAG: BB#0 'main:entry'
SelectionDAG has 18 nodes:
t0: ch = EntryToken
t4: ch = store<ST4[%retval]> t0, Constant:i32<0>,
FrameIndex:i32<0>, undef:i32
t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>,
undef:i32
t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>,
FrameIndex:i32<3>, undef:i32
t12: ch = store<ST4[%m]> t10, Constant:i32<0>, FrameIndex:i32<19>,
und...
2009 Oct 14
14
ZFS disk failure question
...g. But, it had only been running for a few minutes. Evidently, it didn''t start resilvering until I rebooted it. I would have expected it to do that when the disk failed last night (I had set up a hot spare disk already).
All of the zpool commands were taking minutes to complete while c8t7d0 was UNAVAIL, so I offline''d it. When I say all, that includes iostat, status, upgrade, just about anything non-destructive that I could try. That was a little odd. Once I offlined the drive, my resilver restarted, which surprised me. After all, I simply changed an UNAVAIL drive to OF...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...when i use the
> command -view-dag-combine2-dags i get the required output in graph
> but the following error on console:
>
> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x
> i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7,
> t12, undef:i64
> t7: v64i32 = add t6, t4
> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14,
> undef:i64
> t14: i64 = X86ISD::Wrapper TargetGlobalAdd...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...where it goes from
this:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12:...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...39;s going on and found:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12:...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...then when i use the command -view-dag-combine2-dags i
>> get the required output in graph but the following error on console:
>>
>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a
>> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>> t7: v64i32 = add t6, t4
>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...'bclr64:entry'
>> SelectionDAG has 14 nodes:
>> t0: ch = EntryToken
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>>
>> Combining:...
2016 Jun 21
3
LLVM Backend Issues
...time to help me!
Jeff
jeff at ubuntu:~/code$ llc dft_gf_msp.ll
LLVM ERROR: Cannot select: t28: ch = store<ST2[%le](align=4), trunc to i16>
t27, t26, FrameIndex:i32<14>, undef:i32
t26: i32,ch = load<LD2[%sz](align=4), anyext from i16> t25,
FrameIndex:i32<2>, undef:i32
t7: i32 = FrameIndex<2>
t4: i32 = undef
t17: i32 = FrameIndex<14>
t4: i32 = undef
In function: main
LLVMTargetMachine(T, "e-m:e-p:32:32-i8:8:32-i16:16:32-n32-S32", TT, CPU,
FS, Options, RM, CM, OL),
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2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...CopyFromReg t0, Register:i32 %0
t10: i32 = and t2, Constant:i32<65535>
t16: i64 = zero_extend t10
t17: i64 = ctlz t16
t22: i64 = add t17, Constant:i64<-32>
t20: i32 = truncate t22
t15: i32 = add t20, Constant:i32<-16>
t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15
t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1
It seems that SelectionDAG::computeKnownBits() has a case for ISD::CTLZ,
and it seems to figure out that the high bits of t17 are zero, as expected.
t17 is guaranteed to have a value betw...
2017 Jul 29
2
ISelDAGToDAG breaks node ordering
...ect-looking machine instructions, but the node
order is all botched up. For example, given this input:
SelectionDAG has 8 nodes:
t0: ch = EntryToken
t2: i16,ch = CopyFromReg t0, Register:i16 %vreg0
t5: i16,ch = load<Volatile LD2[%1](align=1)(dereferenceable)> t0, t2, undef:i16
t7: ch,glue = CopyToReg t5:1, Register:i16 %R25R24, t5
t8: ch = RET_FLAG t7, Register:i16 %R25R24, t7:1
The resulting output is
SelectionDAG has 8 nodes:
t0: ch = EntryToken
t7: ch,glue = CopyToReg t10:1, Register:i16 %R25R24, t10
t2: i16,ch = CopyFromReg t0, Register:i16 %vreg0
t9:...
2018 Sep 10
2
linear-scan RA
...n terms of liveness
information.
It depends on the details.
For example, given
t0 = mumble
if (something) {
t2 = 3
}
else {
t3 = t0 + 3
print t0
}
t4 = phi(t2, t3)
it's clear that t2 and t0 shouldn't interfere,
but some folks might say the ranges overlap.
Similarly,
t6 = mumble
t7 = t6
t8 = t6 + 5
t9 = t7 + 10
print t8, t9
Chaitin points out that t6 and t7 shouldn't interfere,
even though the live ranges overlap.
Anyway, I'll look at the links.
Thanks,
Preston
>
> We have separate aggressive coalescing pass before allocation. The
> register allocato...
2015 Jun 03
3
[LLVMdev] [lld] TBSS wrong size
...not calculating all sections from all objects. The following example on
x86_64 shows the issue:
--- t0.c ---
#include <stdio.h>
extern __thread int t0;
extern __thread int t1;
extern __thread int t2;
extern __thread int t3;
__thread int t4;
__thread int t5;
__thread int t6;
__thread int t7;
int main ()
{
t4 = 1;
t5 = 2;
t6 = 3;
t7 = 4;
printf ("%i %i %i %i\n", t0, t1, t2, t3);
printf ("%i %i %i %i\n", t4, t5, t6, t7);
return 0;
}
--- t1.c ---
__thread int t0;
__thread int t1;
__thread int t2;
__thread int t3;
-------------
If you build with ll...
2016 Dec 26
2
[SDAG] Recovering pointer types
...ith this as the initial SDAG:
Initial selection DAG: BB#0 'test:entry'
SelectionDAG has 9 nodes:
t0: ch = EntryToken
t3: i64 = Constant<0>
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2, undef:i64
t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5
t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1
What I would like to do is emit efficient code for cases where the
parameter pointer has the same alignment requirements as the load and emit
the conservative but less efficient code in other c...
2016 Dec 26
0
[SDAG] Recovering pointer types
...Initial selection DAG: BB#0 'test:entry'
> SelectionDAG has 9 nodes:
> t0: ch = EntryToken
> t3: i64 = Constant<0>
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2, undef:i64
> t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5
> t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1
>
> What I would like to do is emit efficient code for cases where the parameter pointer has the same alignment requirements as the load and emit the conservative but less efficient...
2009 Mar 18
1
Reading a file line by line - separating lines VS separating columns
...columns, to
which I found a solution but it doesn't feel to be a smart solution, any
ideas or help of how to improve this would be welcomed.
# sample code:
# creating a simple file zz <- file("ex.data", "w") # open an output file
connection cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") (temp.file = scan("ex.data", what = "&q...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...nDAG has 14 nodes:
> t0: ch = EntryToken
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
> t6: i64 = sub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>
>...
2018 Sep 11
2
linear-scan RA
...le
>
> if (something) {
> t2 = 3
> }
> else {
> t3 = t0 + 3
> print t0
> }
> t4 = phi(t2, t3)
>
>
> it's clear that t2 and t0 shouldn't interfere,
> but some folks might say the ranges overlap.
>
>
> Similarly,
>
> t6 = mumble
> t7 = t6
> t8 = t6 + 5
> t9 = t7 + 10
> print t8, t9
>
>
> Chaitin points out that t6 and t7 shouldn't interfere,
> even though the live ranges overlap.
>
> - We go out of SSA form before allocating registers so you won't see phi
> instruction.
> - In the second...
2007 Mar 01
2
[LLVMdev] Version 1.9 SSA form question
int %nlz10(uint %param.x) {
%.t3 = shr uint %param.x, ubyte 1 ; <uint>
[#uses=1]
%.t4 = or uint %.t3, %param.x ; <uint> [#uses=2]
%.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1]
%.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2]
%.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1]
%.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2]
%.t15 = shr...