Displaying 20 results from an estimated 161 matches for "t6".
2010 Apr 14
5
Dovecot 2.0b4 configuration issue, listen config option?
Hi,
In my 1.2 setup I have pop3 running on ip x.x.x.2 and imap on x.x.x.7
In 2.0 how do I say listen x.x.x.2:110 x.x.x.7:143 so that pop3 is not
listening on the .7 ip? I tried putting a listen = ip in the listener
section but it complained. I cant figure it out and cant seem to find
any 2.0 specific documentation, trying to search in the wiki directory
of /usr/local/share/doc/dovecot/wiki but
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...o library calls aren't
maintaining the proper ordering in relation to other chains in the DAG.
The following snippet of a DAG demonstrates the problem.
t0: ch = EntryToken
t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0
t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1
t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1
t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1
t11: ch = CopyToReg t0, Register:i64 %vreg0, t2
t13: ch = CopyToReg t0, Register:i64 %vreg1, t4
t15: ch = CopyToReg t0, Register:i64 %vreg2, t8
t26:...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...n llc with -debug to get a better idea of what's going on and found:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::R...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...re any way to get it to delay this optimization where it goes from
this:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::R...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...i get the required output in graph
> but the following error on console:
>
> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x
> i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7,
> t12, undef:i64
> t7: v64i32 = add t6, t4
> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14,
> undef:i64
> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x
> i32]* @c> 0
>...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...> this:
>>
>> Initial selection DAG: BB#0 'bclr64:entry'
>> SelectionDAG has 14 nodes:
>> t0: ch = EntryToken
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64...
2012 Jul 06
2
[LLVMdev] Excessive register spilling in large automatically generated functions, such as is found in FFTW
...);
zk_d = MULI(SUB(zk_p, zk_n));
*r2 = SUB(uk, zk);
*r0 = ADD(uk, zk);
*r3 = ADD(uk2, zk_d);
*r1 = SUB(uk2, zk_d);
}
__INLINE void L_4_4(const float *i0, const float *i1, const float *i2,
const float *i3, __m128 *r0, __m128 *r1, __m128 *r2, __m128 *r3) {
__m128 t0, t1, t2, t3, t4, t5, t6, t7;
t0 = LOAD(i0);
t1 = LOAD(i1);
t2 = LOAD(i2);
t3 = LOAD(i3);
t4 = ADD(t0, t1);
t5 = SUB(t0, t1);
t6 = ADD(t2, t3);
t7 = MULI(SUB(t2, t3));
t0 = ADD(t4, t6);
t2 = SUB(t4, t6);
t1 = SUB(t5, t7);
t3 = ADD(t5, t7);
TX2(&t0,&t1);
TX2(&t2,&t3);
*r0...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...dags i
>> get the required output in graph but the following error on console:
>>
>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a
>> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>> t7: v64i32 = add t6, t4
>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0
>> t13: i64 = Targ...
2018 Sep 10
2
linear-scan RA
...ou can get in terms of liveness
information.
It depends on the details.
For example, given
t0 = mumble
if (something) {
t2 = 3
}
else {
t3 = t0 + 3
print t0
}
t4 = phi(t2, t3)
it's clear that t2 and t0 shouldn't interfere,
but some folks might say the ranges overlap.
Similarly,
t6 = mumble
t7 = t6
t8 = t6 + 5
t9 = t7 + 10
print t8, t9
Chaitin points out that t6 and t7 shouldn't interfere,
even though the live ranges overlap.
Anyway, I'll look at the links.
Thanks,
Preston
>
> We have separate aggressive coalescing pass before allocation. The
> regis...
2019 Jan 22
2
Different SelectionDAGs for same CPU
...ret i32 %1
}
Before instruction selection, the Selection DAGs are the same:
Optimized legalized selection DAG: %bb.0 '_Z9test_mathv:'
SelectionDAG has 7 nodes:
t0: ch = EntryToken
t4: i32,ch = load<(dereferenceable load 4 from %ir.a)> t0, FrameIndex:i32<0>, undef:i32
t6: ch,glue = CopyToReg t0, Register:i32 $r4, t4
t7: ch = UISD::Ret t6, Register:i32 $r4, t6:1
But after it, one has 1 more node than the other
compiler 1
===== Instruction selection ends:
Selected selection DAG: %bb.0 '_Z9test_mathv:'
SelectionDAG has 8 nodes:
t0: ch = EntryToken...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...ection DAG: BB#0 'bclr64:entry'
> SelectionDAG has 14 nodes:
> t0: ch = EntryToken
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
> t6: i64 = sub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t...
2018 Sep 11
2
linear-scan RA
...t;
> t0 = mumble
>
> if (something) {
> t2 = 3
> }
> else {
> t3 = t0 + 3
> print t0
> }
> t4 = phi(t2, t3)
>
>
> it's clear that t2 and t0 shouldn't interfere,
> but some folks might say the ranges overlap.
>
>
> Similarly,
>
> t6 = mumble
> t7 = t6
> t8 = t6 + 5
> t9 = t7 + 10
> print t8, t9
>
>
> Chaitin points out that t6 and t7 shouldn't interfere,
> even though the live ranges overlap.
>
> - We go out of SSA form before allocating registers so you won't see phi
> instruction.
>...
2015 Jun 03
3
[LLVMdev] [lld] TBSS wrong size
...tbss section
and not calculating all sections from all objects. The following example on
x86_64 shows the issue:
--- t0.c ---
#include <stdio.h>
extern __thread int t0;
extern __thread int t1;
extern __thread int t2;
extern __thread int t3;
__thread int t4;
__thread int t5;
__thread int t6;
__thread int t7;
int main ()
{
t4 = 1;
t5 = 2;
t6 = 3;
t7 = 4;
printf ("%i %i %i %i\n", t0, t1, t2, t3);
printf ("%i %i %i %i\n", t4, t5, t6, t7);
return 0;
}
--- t1.c ---
__thread int t0;
__thread int t1;
__thread int t2;
__thread int t3;
-------------
If...
2005 Jun 27
2
simplifying the code
...5),b=seq(1000,1005))
I want to add a new column dat$c in that:
t1<-ifelse(dat$a==1&dat$b==1001,1001,0)
t2<-ifelse(dat$a==2&dat$b==1002,1001,0)
t3<-ifelse(dat$a==3&dat$b==1003,1001,0)
t4<-ifelse(dat$a==1&dat$b==1002,1002,0)
t5<-ifelse(dat$a==2&dat$b==1003,1002,0)
t6<-ifelse(dat$a==1&dat$b==1003,1003,0)
dat$c<-t1+t2+t3+t4+t5+t6
My real data frame is much larger... I hope someone
can help me with this.
thanks for your help
a. diaz
-------------------------------------------------
Email Enviado utilizando o servi佺o MegaMail
2006 Nov 20
4
how to use the switch statement
Good morning,
I am trying to recode the values of a column in a data frame and,
instead of using a long series of if/else statements I would like to use
a switch (as it is, for instance, in the C programming language).
I have a column of this type:
AT
BB
B1
B1
CC
CC
T6
B1
CC
BB
TT
AT
AT
AT
TT
BB
...
and I need to change this coding (if it's AT then it should be A1, if
it's BB then it should be A2, and so on ...)
I was trying to use switch in the following way:
switch(column_name,
'AT'='A1'
'BB'='A2'
...)
but it'...
2010 Nov 23
2
[LLVMdev] Unrolling an arithmetic expression inside a loop
...ected from cfe-dev, as code optimizations in clang are
done in llvm layer.
I'm investigating how optimized code clang generates, and have come
across such an example:
I have two procedures:
void exec0(const int *X, const int *Y, int *res, const int N) {
int t1[N],t2[N],t3[N],t4[N],t5[N],t6[N];
for(int i = 0; i < N; i++) {
t1[i] = X[i]+Y[i]; // X+Y
t2[i] = t1[i]*Y[i]; // XY + Y2
t3[i] = X[i]*Y[i]; // XY
t4[i] = Y[i]*Y[i]; // Y2
t5[i] = t3[i]+t4[i]; // XY + Y2
t6[i] = t2[i]-t5[i];...
2009 Mar 18
1
Reading a file line by line - separating lines VS separating columns
...ng columns, to
which I found a solution but it doesn't feel to be a smart solution, any
ideas or help of how to improve this would be welcomed.
# sample code:
# creating a simple file zz <- file("ex.data", "w") # open an output file
connection cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") (temp.file = scan("ex.data", what = "...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
Hi,
I am having some issues with how some of the instructions are being
legalized.
So this is my intial basic block. The area of concern is the last three
instructions. I will pick and choose debug output to keep this small.
SelectionDAG has 36 nodes:
t0: ch = EntryToken
t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
t4: i32 = or t2, Constant:i32<256>
t9: i32 = shl t4, Constant:i32<2>
t10: i32 = add t6, t9
t12: i32,ch = CopyFromReg t0, Register:i32 %vr...
2018 Sep 11
2
linear-scan RA
...gt;>> t3 = t0 + 3
>>> print t0
>>> }
>>> t4 = phi(t2, t3)
>>>
>>> it's clear that t2 and t0 shouldn't interfere,
>>> but some folks might say the ranges overlap.
>>>
>>> Similarly,
>>>
>>> t6 = mumble
>>> t7 = t6
>>> t8 = t6 + 5
>>> t9 = t7 + 10
>>> print t8, t9
>>>
>>> Chaitin points out that t6 and t7 shouldn't interfere,
>>> even though the live ranges overlap.
>>
>> - We go out of SSA form before alloca...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...e instructions are being
>> legalized.
>> So this is my intial basic block. The area of concern is the last three
>> instructions. I will pick and choose debug output to keep this small.
>>
>> SelectionDAG has 36 nodes:
>> t0: ch = EntryToken
>> t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
>> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
>> t4: i32 = or t2, Constant:i32<256>
>> t9: i32 = shl t4, Constant:i32<2>
>> t10: i32 = add t6, t9
>> t...