Displaying 2 results from an estimated 2 matches for "t2stri12".
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2020 Sep 07
2
Metadata in LLVM back-end
Am 31/08/20 um 14:10 schrieb David Greene:
> Lorenzo Casalino via llvm-dev <llvm-dev at lists.llvm.org> writes:
>
>> Furthermore, after register allocation there is a non-negligible effort
>> to properly annotate instructions which share the same output register...
>>
>> Concerning the usage of the live ranges to tie annotated instruction and
>> intrinsic,
2020 Sep 15
2
Metadata in LLVM back-end
...te* predecessor of (K) in the
instruction stream).
For instance, assume to have the following SSA stream (I am using the
ARM Thumb2
MIR since I've been working mainly on that backend):
#i %res = t2ANDrr %src_1_i, %src_2_i
...
#j %null = llvm.metadata %a, (some metadata)
...
#l %c = t2STRi12 %res, %stack_slot_res
Where instruction #l kills the live-range representing %res, and
instructions
#j is covered by the live-range of %res, which spans from #i to #l.
Giving a total ordering to the stream of instructions, #i <= #j <= #l.
As you can infer, intrinsic represented by instructi...