search for: t22

....then, label %if.else (compiled with: clang -O0 -emit-llvm -S failing.c -o failing.ll ) I reran passing -debug to llc to see what's happening at various stages of DAG optimization: clang -O0 -mllvm -debug -S failing.c -o failing.s The initial selection DAG has the AND op node: t22: i8 = srl t19, Constant:i64<1> * t23: i8 = and t22, Constant:i8<1>* t24: i32 = zero_extend t23 t27: i1 = setcc t24, Constant:i32<1>, seteq:ch t29: i1 = xor t27, Constant:i1<-1> t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d...

...ang -O0 -emit-llvm -S failing.c -o failing.ll ) > > I reran passing -debug to llc to see what's happening at various > stages of DAG optimization: > > clang -O0 -mllvm -debug -S failing.c -o failing.s > > The initial selection DAG has the AND op node: > > t22: i8 = srl t19, Constant:i64<1> > * t23: i8 = and t22, Constant:i8<1>* > t24: i32 = zero_extend t23 > t27: i1 = setcc t24, Constant:i32<1>, seteq:ch > t29: i1 = xor t27, Constant:i1<-1> > t31: ch = brcond t18, t29, BasicBl...

...lang -O0 -emit-llvm -S failing.c -o failing.ll ) > > I reran passing -debug to llc to see what's happening at various stages of > DAG optimization: > > clang -O0 -mllvm -debug -S failing.c -o failing.s > > The initial selection DAG has the AND op node: > > t22: i8 = srl t19, Constant:i64<1> > * t23: i8 = and t22, Constant:i8<1>* > t24: i32 = zero_extend t23 > t27: i1 = setcc t24, Constant:i32<1>, seteq:ch > t29: i1 = xor t27, Constant:i1<-1> > t31: ch = brcond t18, t29, BasicBl...

...rogress on this. Thank you >From your description it seems like you are seeing an incorrect behavior. If that's the case, it should definitely be fixed. Could you provide the complete DAG before and after the erroneous transformation? -Krzysztof Combining: t25: v2i16 = BUILD_VECTOR t27, t22 Before reduceBuildVecToShuffle SelectionDAG has 14 nodes: t0: ch = EntryToken t2: v4i16,ch = CopyFromReg t0, Register:v4i16 %0 // [a b c d] t26: v2i16 = extract_subvector t2, Constant:i32<0> // [a b] t27: i16 = extract_vector_elt t26, Constant:i32<0> // [a]...

...t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1] %.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2] %.t19 = shr uint %.t16, ubyte 16 ; <uint> [#uses=1] %.t20 = or uint %.t19, %.t16 ; <uint> [#uses=1] %.t22 = mul uint %.t20, 116069625 ; <uint> [#uses=1] %.t25 = shr uint %.t22, ubyte 26 ; <uint> [#uses=1] %.t28 = getelementptr [64 x ubyte]* %table, int 0, uint %.t25 ; <ubyte*> [#uses=1] %.t28 = load ubyte* %.t28 ; <...

...timized DAG as input to instruction selection: SelectionDAG has 15 nodes:   t0: ch = EntryToken                 t2: i32,ch = CopyFromReg t0, Register:i32 %0               t10: i32 = and t2, Constant:i32<65535>             t16: i64 = zero_extend t10           t17: i64 = ctlz t16         t22: i64 = add t17, Constant:i64<-32>       t20: i32 = truncate t22     t15: i32 = add t20, Constant:i32<-16>   t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15   t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1 It seems that SelectionDAG::computeKnownBits() has a case for I...

...: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt...

SYSLINUX 4.00 2010-06-28 EDD Load error - Boot error Booting from USB on old IBM T43 or newer Esprimo E5731E. No problems with version 3.86 and same usb-stick.

..., I am having a data for 2 different treatments with different time points. So, I used the following code to plot the boxplot and also to do anova. T11 <- c(280, 336, 249, 277, 429) T12 <- c(400, 397, 285, 407, 313) T13 <- c(725, 373, 364, 706, 249) T21 <- c(589, 257, 466, 248, 913) T22 <- c(519, 424, 512, 298, 907) T23 <- c(529, 479, 634, 354, 1015) obs <- c(T11, T12, T13, T21, T22, T23) treat <- c(rep("T1",15), rep("T2",15)) time <- c(rep("one",5), rep("two",5), rep("thr",5), rep("one",5), re...

...help on this? Paul ================================================= I want to be able to create a design matrix with two factors. For instance, if I have: > t1 <- factor(c(1,1,2,2)); > t2 <- factor(c(1,2,1,2)); > design <- model.matrix(~ -1 + (t1+t2)); > design; t11 t12 t22 1 1 0 0 2 1 0 1 3 0 1 0 4 0 1 1 But the design matrix I want is: t1 t2 1 1 0 2 1 1 3 0 0 4 0 1 Actually, in general I'm struggling with the syntax for formulating a design matrix I can write down on paper. Is there a reference for this beyond the R do...

...Constant:i64<4>, Constant:i64<5>, Constant:i64<6>, Constant:i64<7> t16: v8i64 = add t7, t15 t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16 t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5 t22: i64 = AssertSext t20, ValueType:ch:i8 t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0> t24: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t23, undef:v8i64 t32: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64&...

...; t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 > t7: i32 = AssertZext t5, ValueType:ch:i1 > t8: v2i32 = BUILD_VECTOR t2, t7 > t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> > t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 > t22: i32 = add t15, Constant:i32<1> > t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 > t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> > t31: ch = TokenFactor t24, t27 > t13: v2i1 = setcc t8, t11, setne:ch > t16: i1...

...n you load a value whose size in bits is not a multiple of 8 (like i1, or <4 x i1>, the result is undefined unless the unused bits are zero. You can see this in the debug output from llc: SelectionDAG has 15 nodes: t0: ch = EntryToken t21: i32 = X86ISD::KORTEST t19, t19 t22: i8 = X86ISD::SETCC Constant:i8<4>, t21 t23: i32 = zero_extend t22 t14: ch,glue = CopyToReg t0, Register:i32 %EAX, t23 t24: i16,ch = load<LD1[%XXX](align=4)(dereferenceable), zext from i8> t0, FrameIndex:i64<0>, undef:i64 t26: i16 = AssertZext t24, ValueType:c...

...: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt...

I see we're missing an isel pattern for add producing carry and doing a memory RMW. I'm going to see if adding that helps anything. ~Craig On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes. I'm seeing that as well. Not clear what's going on. > > In any case it looks to be unrelated to the alias analysis so barring

...ch = CopyToReg t0, Register:i16 %4, t13 Creating new node: t17: i16,ch = CopyFromReg t0, Register:i16 %0 Creating constant: t18: i16 = Constant<-1> Creating new node: t19: i16 = add t17, Constant:i16<-1> Creating new node: t21: ch = CopyToReg t0, Register:i16 %5, t19 Creating new node: t22: ch = TokenFactor t12, t15, t21, t8 Creating new node: t24: ch = br t22, BasicBlock:ch<for.cond 0x10985e000> Initial selection DAG: %bb.3 'tst:for.body' SelectionDAG has 25 nodes: t0: ch = EntryToken t2: i16,ch = CopyFromReg t0, Register:i16 %1 t3: i16 = Constant<0> t5:...

...sson()) on data from Jim Lindsey's book : change count t1 t2 1 45 1 1 2 13 1 2 3 12 2 1 4 54 2 2 I get : Call: glm(formula = change$count ~ change$t1 * change$t2, family = poisson()) Coefficients: (Intercept) change$t12 change$t22 3.807 -1.322 -1.242 change$t12.change$t22 2.746 Degrees of Freedom: 3 Total (i.e. Null); 0 Residual Null Deviance: 48.11 Residual Deviance: 6.596e-16 AIC: 28.23 My question is : how the AIC value is computed here? Because t...

Hello, I am getting this error. What instruction is required to be implemented? LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16 t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>, undef:i64 t659: i64 = FrameIndex<1> t10: i64 = undef t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0, t8, undef:i64 t8: i64 = ad...

...: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt...

...John Hi, I've been messing with getting SIP working for days now, with limited success. I've got Asterisk set up on a remote server with the echo test. Please try it out to verify I've got the server working right: sip:robot at nixon.butchwax.com Running FC1, ThinkPad T22, headset thru the soundcard. Asterisk is asterisk-1.0_RC1. No NAT. The phones I've tried so far are as follows. ** Linphone: Check out my SRPM at http://www.bigu.org/SRPMS/ Sound is fine. Doesn't seem to pick up anything from the microphone, though. ** kphone: Check out my SRPM at...