search for: t19

...B#0 'main:entry' SelectionDAG has 18 nodes: t0: ch = EntryToken t4: ch = store<ST4[%retval]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32 t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>, undef:i32 t19: ch = store<ST4[%dir]> t7, Constant:i32<-1082130432>, FrameIndex:i32<3>, undef:i32 t12: ch = store<ST4[%m]> t19, Constant:i32<0>, FrameIndex:i32<19>, undef:i32 t13: i32,ch = load<LD4[%sz]> t12, FrameIndex:i32<2>, undef:i32 t15: ch = store&lt...

...vector_elt t26, Constant:i32<0> // [a] t21: v2i16 = extract_subvector t2, Constant:i32<2> //[c d] t22: i16 = extract_vector_elt t21, Constant:i32<0> // [c] t25: v2i16 = BUILD_VECTOR t27, t22 // [a c] t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25 t19: ch = RTN t18 t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1 Creating new node: t28: v2i16 = undef Creating new node: t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16 After reduceBuildVecToShuffle SelectionDAG has 16 nodes: t0: ch = EntryToken t2: v4i16,ch = CopyFro...

...if.else (compiled with: clang -O0 -emit-llvm -S failing.c -o failing.ll ) I reran passing -debug to llc to see what's happening at various stages of DAG optimization: clang -O0 -mllvm -debug -S failing.c -o failing.s The initial selection DAG has the AND op node: t22: i8 = srl t19, Constant:i64<1> * t23: i8 = and t22, Constant:i8<1>* t24: i32 = zero_extend t23 t27: i1 = setcc t24, Constant:i32<1>, seteq:ch t29: i1 = xor t27, Constant:i1<-1> t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48> t33:...

...llvm -S failing.c -o failing.ll ) > > I reran passing -debug to llc to see what's happening at various > stages of DAG optimization: > > clang -O0 -mllvm -debug -S failing.c -o failing.s > > The initial selection DAG has the AND op node: > > t22: i8 = srl t19, Constant:i64<1> > * t23: i8 = and t22, Constant:i8<1>* > t24: i32 = zero_extend t23 > t27: i1 = setcc t24, Constant:i32<1>, seteq:ch > t29: i1 = xor t27, Constant:i1<-1> > t31: ch = brcond t18, t29, BasicBlock:ch<if.e...

...%.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1] %.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2] %.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1] %.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2] %.t19 = shr uint %.t16, ubyte 16 ; <uint> [#uses=1] %.t20 = or uint %.t19, %.t16 ; <uint> [#uses=1] %.t22 = mul uint %.t20, 116069625 ; <uint> [#uses=1] %.t25 = shr uint %.t22, ubyte 26 ; <uint> [#uses=...

Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help

...g t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt t13, t15 t17: i32 = extract_vector_elt t8, t15 t18: i32 = extract_vector_elt t11, t15 t19: i1 = setcc t17, t18, setne:ch t20: i1 = xor t16, t19 ... I have not added any vector register class so 'DAGTypeLegalizer' tries to split the "t16: i1 = extract_vector_elt t13, t15" because t13's result type is 'v2i1'. If the size of vector element is les...

...y the load. When you load a value whose size in bits is not a multiple of 8 (like i1, or <4 x i1>, the result is undefined unless the unused bits are zero. You can see this in the debug output from llc: SelectionDAG has 15 nodes: t0: ch = EntryToken t21: i32 = X86ISD::KORTEST t19, t19 t22: i8 = X86ISD::SETCC Constant:i8<4>, t21 t23: i32 = zero_extend t22 t14: ch,glue = CopyToReg t0, Register:i32 %EAX, t23 t24: i16,ch = load<LD1[%XXX](align=4)(dereferenceable), zext from i8> t0, FrameIndex:i64<0>, undef:i64 t26: i16 = AssertZext...

...-llvm -S failing.c -o failing.ll ) > > I reran passing -debug to llc to see what's happening at various stages of > DAG optimization: > > clang -O0 -mllvm -debug -S failing.c -o failing.s > > The initial selection DAG has the AND op node: > > t22: i8 = srl t19, Constant:i64<1> > * t23: i8 = and t22, Constant:i8<1>* > t24: i32 = zero_extend t23 > t27: i1 = setcc t24, Constant:i32<1>, seteq:ch > t29: i1 = xor t27, Constant:i1<-1> > t31: ch = brcond t18, t29, BasicBlock:ch<if.e...

...= distinct !{!3, !4, !5} !4 = !{!"llvm.loop.vectorize.width", i32 1} !5 = !{!"llvm.loop.interleave.count", i32 1} !6 = distinct !{!6, !2} !7 = distinct !{!7, !4, !5} I get the following error: LLVM ERROR: Cannot select: t21: ch = store<ST64[%6](align=4)> t20, t19, t6, undef:i64 I don't understand why because it seems to me store is specified well in [MyTarget]InstrInfo.td . Can somebody help with an idea? Myself I will try to debug the code generated with TableGen, implementing the function SelectCode() . Best regards, Alex

...a thread local storage (notice TLS in the name). > > The same result can be reproduced by this simple program: > > thread_local int x = 0; > int main() { > return 0; > } > >When compiled into IR it produces similar error: > >LLVM ERROR: Cannot select: t19: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=19] > t18: i64 = TargetGlobalTLSAddress<i32* @x> 0 [TF=19] >In function: _ZTW1x interestingly this works on my machine. llvm-ir attached 2017-02-07 15:31 GMT+00:00 Alex Denisov <1101.debian at gmail.com&g...

...ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16 Creating constant: t13: i16 = Constant<1> Creating new node: t14: i16 = add nuw nsw t4, Constant:i16<1> Creating new node: t16: ch = CopyToReg t0, Register:i16 %1, t14 Creating new node: t17: ch = TokenFactor t16, t12 Creating new node: t19: ch = br t17, BasicBlock:ch<for.cond 0x10983ff38> Initial selection DAG: %bb.3 'tst:for.body' SelectionDAG has 20 nodes: t0: ch = EntryToken t4: i16,ch = CopyFromReg t0, Register:i16 %0 t6: i16 = Constant<0> t2: i16,ch = CopyFromReg t0, Register:i16 %3 t5: i16 =...

...8, Constant:i32<-1> > t31: ch = TokenFactor t24, t27 > t13: v2i1 = setcc t8, t11, setne:ch > t16: i1 = extract_vector_elt t13, t15 > t17: i32 = extract_vector_elt t8, t15 > t18: i32 = extract_vector_elt t11, t15 > t19: i1 = setcc t17, t18, setne:ch > t20: i1 = xor t16, t19 > > ... > > I have not added any vector register class so 'DAGTypeLegalizer' tries > to split the "t16: i1 = extract_vector_elt t13, t15" because t13's > result type is 'v2i1'. If t...

>>>>> <seifried@seifried.org> writes: > I was looking around for a book specifically on Linux security a week or > two ago, and couldn''t find any. I wanted something Linux specific as > opposed to say O''Reilly''s yellow safe book. There are actually Linux-specific details in Practical; I put some of them there. They are not, however,

I have the following selection DAG: SelectionDAG has 9 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15

...tadata !16), !dbg !17 tail call void @h(i16 %call) #2, !dbg !18 ret void, !dbg !19 } For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0. t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11 t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11 t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, test.c:5:11 Then, TargetLowering::LowerCallTo adds a truncate node since the function return type is i16. t21: i16 = truncate t20...

...g t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt t13, t15 t17: i32 = extract_vector_elt t8, t15 t18: i32 = extract_vector_elt t11, t15 t19: i1 = setcc t17, t18, setne:ch t20: i1 = xor t16, t19 ... I have not added any vector register class so 'DAGTypeLegalizer' tries to split the "t16: i1 = extract_vector_elt t13, t15" because t13's result type is 'v2i1'. If the size of vector element is...

...0} (gdb) print Vals[3] $4 = {Node = 0x6c18b0, ResNo = 0} Before i-sel started, store had as inputs a TokenFactor, an add, a CopyFromReg (I can provide the entire DOT output with -view-isel-dags) and an undef. If we give during i-sel, at InitOperands(): (gdb) print Ops[0].Val.Node->dump()t19: v8i64 = add t18, t17 So, Ops[0] is add. So, the problem is that after instruction selection of a RET, CopyToReg and TokenFactor I have a messed-up SelectionDAG, with the problems mentioned above for the select instruction that cause the segfault. Did anybody encounter a similar p...

I see we're missing an isel pattern for add producing carry and doing a memory RMW. I'm going to see if adding that helps anything. ~Craig On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes. I'm seeing that as well. Not clear what's going on. > > In any case it looks to be unrelated to the alias analysis so barring

...l void @h(i16 %call) #2, !dbg !18 > ret void, !dbg !19 > } > > For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0. > > t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11 > t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11 > t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, test.c:5:11 > > Then, TargetLowering::LowerCallTo adds a truncate node since the function return type is i16. > >...