Displaying 20 results from an estimated 40 matches for "t17".
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2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...ret i16 %1
}
,gives this optimized DAG as input to instruction selection:
SelectionDAG has 15 nodes:
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t10: i32 = and t2, Constant:i32<65535>
t16: i64 = zero_extend t10
t17: i64 = ctlz t16
t22: i64 = add t17, Constant:i64<-32>
t20: i32 = truncate t22
t15: i32 = add t20, Constant:i32<-16>
t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15
t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1
It seems that SelectionDAG::comput...
2016 Jun 22
2
LLVM Backend Issues
...t;,
FrameIndex:i32<3>, undef:i32
t12: ch = store<ST4[%m]> t10, Constant:i32<0>, FrameIndex:i32<19>,
undef:i32
t13: i32,ch = load<LD4[%sz]> t12, FrameIndex:i32<2>, undef:i32
t15: ch = store<ST4[%j]> t13:1, t13, FrameIndex:i32<16>, undef:i32
t17: ch = store<ST4[%le]> t15, t13, FrameIndex:i32<14>, undef:i32
Optimized lowered selection DAG: BB#0 'main:entry'
SelectionDAG has 18 nodes:
t0: ch = EntryToken
t4: ch = store<ST4[%retval]> t0, Constant:i32<0>,
FrameIndex:i32<0>, undef:i3...
2016 Sep 03
4
llc error
Hi all,
The attached LLVM assembly file fails to generate x86 code when compiled
using llc.
compilation command - ../llvm-build/bin/llc -filetype=asm -march=x86-64
-mcpu=core-avx2 ex4.ll
The error message is,
LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17
t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16, undef:i64
t16: i64 = add t2, Constant:i64<16>
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5
t1: i64 = Register %vreg5
t15: i64 = Constant<16>
t4: i64 = undef
In function: _ZN10so...
2016 Jun 21
3
LLVM Backend Issues
...ft_gf_msp.ll
LLVM ERROR: Cannot select: t28: ch = store<ST2[%le](align=4), trunc to i16>
t27, t26, FrameIndex:i32<14>, undef:i32
t26: i32,ch = load<LD2[%sz](align=4), anyext from i16> t25,
FrameIndex:i32<2>, undef:i32
t7: i32 = FrameIndex<2>
t4: i32 = undef
t17: i32 = FrameIndex<14>
t4: i32 = undef
In function: main
LLVMTargetMachine(T, "e-m:e-p:32:32-i8:8:32-i16:16:32-n32-S32", TT, CPU,
FS, Options, RM, CM, OL),
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2016 Nov 03
2
rotl: undocumented LLVM instruction?
...... into: t15: i64 = rotl Constant:i64<-2>, t6
...to this:
Optimized lowered selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 13 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t17: i64 = add t4, Constant:i64<-1>
t15: i64 = rotl Constant:i64<-2>, t17
t10: i64 = and t2, t15
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
That combining of the xor & and there ends up giving us suboptimal resu...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...ombining: t9: i64 = xor t7, Constant:i64<-1>
... into: t15: i64 = rotl Constant:i64<-2>, t6
Combining: t10: i64 = and t2, t15
Combining: t15: i64 = rotl Constant:i64<-2>, t6
Combining: t14: i64 = Constant<-2>
Combining: t6: i64 = sub t4, Constant:i64<1>
... into: t17: i64 = add t4, Constant:i64<-1>
Combining: t15: i64 = rotl Constant:i64<-2>, t17
These rotl instructions weren't showing up when I ran llc 3.6 and that's
completely changing the generated code at the end which means the test
fails (and it's less optimal than it was in 3....
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...his:
>>
>> Optimized lowered selection DAG: BB#0 'bclr64:entry'
>> SelectionDAG has 13 nodes:
>> t0: ch = EntryToken
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t17: i64 = add t4, Constant:i64<-1>
>> t15: i64 = rotl Constant:i64<-2>, t17
>> t10: i64 = and t2, t15
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>> That combining...
2019 Jun 05
2
Strange behaviour of post-legalising optimisations(?)
...ating new node: t12: ch = store<(store 1 into %ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16
Creating constant: t13: i16 = Constant<1>
Creating new node: t14: i16 = add nuw nsw t4, Constant:i16<1>
Creating new node: t16: ch = CopyToReg t0, Register:i16 %1, t14
Creating new node: t17: ch = TokenFactor t16, t12
Creating new node: t19: ch = br t17, BasicBlock:ch<for.cond 0x10983ff38>
Initial selection DAG: %bb.3 'tst:for.body'
SelectionDAG has 20 nodes:
t0: ch = EntryToken
t4: i16,ch = CopyFromReg t0, Register:i16 %0
t6: i16 = Constant<0>
t2: i16,c...
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...nt:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t...
2016 Sep 03
2
llc error
...s to generate x86 code when compiled
>> using llc.
>>
>> compilation command - ../llvm-build/bin/llc -filetype=asm -march=x86-64
>> -mcpu=core-avx2 ex4.ll
>>
>> The error message is,
>>
>> LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17
>> t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16,
>> undef:i64
>> t16: i64 = add t2, Constant:i64<16>
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5
>> t1: i64 = Register %vreg5
>> t15: i64 = Const...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...selection DAG: BB#0 'bclr64:entry'
> SelectionDAG has 13 nodes:
> t0: ch = EntryToken
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
> t17: i64 = add t4, Constant:i64<-1>
> t15: i64 = rotl Constant:i64<-2>, t17
> t10: i64 = and t2, t15
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>...
2018 Apr 09
2
A way to opt out of a dag combine?
...lements [0, 0]. The problem seems to be treating extract_subvector with
different constants as instances of the same value.
t14: v2f16 = extract_subvector t2, Constant:i32<2>
t15: f16 = extract_vector_elt t14, Constant:i32<0>
t16: v2f16 = extract_subvector t2, Constant:i32<0>
t17: f16 = extract_vector_elt t16, Constant:i32<0>
t9: v2f16 = BUILD_VECTOR t17, t15
... into: t19: v2f16 = vector_shuffle<0,0> t16, undef:v2f16 // fail
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2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
> t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
> t31: ch = TokenFactor t24, t27
> t13: v2i1 = setcc t8, t11, setne:ch
> t16: i1 = extract_vector_elt t13, t15
> t17: i32 = extract_vector_elt t8, t15
> t18: i32 = extract_vector_elt t11, t15
> t19: i1 = setcc t17, t18, setne:ch
> t20: i1 = xor t16, t19
>
> ...
>
> I have not added any vector register class so 'DAGTypeLegalizer' tries
> to split the &...
2019 Feb 09
2
Question about pattern matching process
...o false predicate) at index 3273, continuing at 3284
Skipped scope entry (due to false predicate) at index 3285, continuing at 3305
Match failed at index 3259
Continuing at 3306
Match failed at index 3307
Continuing at 3327
Match failed at index 3328
Continuing at 3361
Morphed node: t17: i32 = MOVRR t17
ISEL: Match complete!
Thanks.
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2002 May 12
1
tinc version 1.0pre7 hangs
...be repeated at will.
I prepared a series of text files with varying numbers of lines. Each
line is:
!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdef
ghijklmn
wc t*.txt
15 15 1200 t15.txt
16 16 1280 t16.txt
17 17 1360 t17.txt
18 18 1440 t18.txt
20 20 1600 t20.txt
30 30 2400 t30.txt
40 40 3200 t40.txt
>From a client system:
telnet 192.168.200.254 (the hub)
cat t16.txt (works)
cat t17.txt (fails, hangs)
I set the debug level to 5 and watched the logs on both...
2016 Jul 29
2
Help with ISEL matching for an SDAG
I have the following selection DAG:
SelectionDAG has 9 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0,
t2, undef:i64
t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16,
t16, t16, t16, t16, t16, t16, t16
t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
2018 Dec 17
4
In ISel, where Constant<0> comes from?
...oca i32, align 4
%argv.addr = alloca i8**, align 8
store i32 0, i32* %retval, align 4
store i32 %argc, i32* %argc.addr, align 4
store i8** %argv, i8*** %argv.addr, align 8
ret i32 0
}
using `llc -march=sparc -debug-only=isel`.
In the Initial selection DAG I see
t19: ch,glue = CopyToReg t17, Register:i32 $i0, Constant:i32<0>
line. The same "Constant:i32<0>" node I see in my toy backend, which forces
me to add a pattern that lowers it using "xor reg,reg". Much like "or
g0,g0" pattern in SPARC.
However, I don't see that Constant node when...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...nt:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_e...
2024 Jan 11
1
No suspend after update
Just updated CentOS 9 Stream on a Lenovo T17 Gen 4 Intel and not it
won't suspend with the following error:
[ 52.604998] Restarting kernel threads ... done.
[ 52.605111] OOM killer enabled.
[ 52.605111] Restarting tasks ... done.
[ 52.606604] random: crng reseeded on system resumption
[ 52.616014] thermal thermal_zone9: failed...
2024 Jan 12
1
No suspend after update
On Wed, Jan 10, 2024 at 11:57?PM Michael B Allen <ioplex at gmail.com> wrote:
>
> Just updated CentOS 9 Stream on a Lenovo T17 Gen 4 Intel and now it
> won't suspend with the following error:
...
> [ 72.805437] Freezing of tasks failed after 20.006 seconds (1 tasks
> refusing to freeze, wq_busy=0):
> [ 72.805450] task:NFSv4 callback state:I stack:0 pid:2191
> ppid:2 flags:0x00004000
FYI
A...