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2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = se...
2016 Jun 22
2
LLVM Backend Issues
...:i32 t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>, FrameIndex:i32<3>, undef:i32 t12: ch = store<ST4[%m]> t10, Constant:i32<0>, FrameIndex:i32<19>, undef:i32 t13: i32,ch = load<LD4[%sz]> t12, FrameIndex:i32<2>, undef:i32 t15: ch = store<ST4[%j]> t13:1, t13, FrameIndex:i32<16>, undef:i32 t17: ch = store<ST4[%le]> t15, t13, FrameIndex:i32<14>, undef:i32 Optimized lowered selection DAG: BB#0 'main:entry' SelectionDAG has 18 nodes: t0: ch = EntryToken t4: ch = store...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...SD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64 = xor t7, Constant:i64<-1> ... into: t15: i64 = rotl Constant:i64<-2>, t6 Combining: t10: i64 = and t2, t15 Combining: t15: i64 = rotl Constant:i64<-2>, t6 Combining: t14: i64 = Constant<-2> Combining: t6: i64 = sub t4, Constant:i64<1> ... into: t17: i64 = add t4, Constant:i64<-1> Combining: t15: i64 =...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...FromReg t0, Register:i32 %vreg0 > t3: ch = ValueType:i32 > t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 > t7: i32 = AssertZext t5, ValueType:ch:i1 > t8: v2i32 = BUILD_VECTOR t2, t7 > t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> > t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 > t22: i32 = add t15, Constant:i32<1> > t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 > t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> > t31: ch = TokenFactor t24, t27 >...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...SD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64 = xor t7, Constant:i64<-1> ... into: t15: i64 = rotl Constant:i64<-2>, t6 ...to this: Optimized lowered selection DAG: BB#0 'bclr64:entry' SelectionDAG has 13 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t17: i64 = add...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
..., Register:i64 %R1, t12:1 >> >> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 >> >> Combining: t11: i64 = Register %R1 >> >> Combining: t10: i64 = and t2, t9 >> >> Combining: t9: i64 = xor t7, Constant:i64<-1> >> ... into: t15: i64 = rotl Constant:i64<-2>, t6 >> >> ...to this: >> >> Optimized lowered selection DAG: BB#0 'bclr64:entry' >> SelectionDAG has 13 nodes: >> t0: ch = EntryToken >> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 >> t...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = se...
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0, Register:i64 %vreg1, t4 t15: ch = CopyToReg t0, Register:i64 %vreg2, t8 t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t8:1 t16: i64 = sdiv t2, t4 Before legalization, there is a single sdiv node. After legalization, this has been expanded to a call sequence: t0: ch = EntryToken t2: i64,ch,glue = Cop...
2016 Jun 21
3
LLVM Backend Issues
Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...1 > > Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 > > Combining: t11: i64 = Register %R1 > > Combining: t10: i64 = and t2, t9 > > Combining: t9: i64 = xor t7, Constant:i64<-1> > ... into: t15: i64 = rotl Constant:i64<-2>, t6 > > ...to this: > > Optimized lowered selection DAG: BB#0 'bclr64:entry' > SelectionDAG has 13 nodes: > t0: ch = EntryToken > t2: i64,ch = CopyFromReg t0, Register...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = se...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...pyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 t4: i32 = or t2, Constant:i32<256> t9: i32 = shl t4, Constant:i32<2> t10: i32 = add t6, t9 t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 t20: i32 = AssertZext t18, ValueType:ch:i1 t23: i1 = setcc t20, Consta...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 >> t4: i32 = or t2, Constant:i32<256> >> t9: i32 = shl t4, Constant:i32<2> >> t10: i32 = add t6, t9 >> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 >> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 >> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 >> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 >> t20: i32 = AssertZext t18, ValueType:ch:i1 >>...
2007 Mar 01
2
[LLVMdev] Version 1.9 SSA form question
...%.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1] %.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2] %.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1] %.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2] %.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1] %.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2] %.t19 = shr uint %.t16, ubyte 16 ; <uint> [#uses=1] %.t20 = or uint %.t19, %.t16 ; <uint> [#uses=1] %.t22...
2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...: ch = EntryToken                 t2: i32,ch = CopyFromReg t0, Register:i32 %0               t10: i32 = and t2, Constant:i32<65535>             t16: i64 = zero_extend t10           t17: i64 = ctlz t16         t22: i64 = add t17, Constant:i64<-32>       t20: i32 = truncate t22     t15: i32 = add t20, Constant:i32<-16>   t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15   t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1 It seems that SelectionDAG::computeKnownBits() has a case for ISD::CTLZ, and it seems to figure out that the high bits of t17 are zero, as exp...
2016 Jul 29
2
Help with ISEL matching for an SDAG
I have the following selection DAG: SelectionDAG has 9 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15 t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1 and the following pattern that I'd like to match: def ScalarLoads { dag Li8...
2020 Feb 22
2
COPYs between register classes
Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t4: i32 = Constant<0> t3: i64,ch = CopyFromReg t0, Register:i64 %vreg12 t6: v8i64 = insert_vector_elt undef:v8i64, t3, Constant:i64<0> t7: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t6, undef:v8i64 t15: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<1>, Constant:i64<2>, Constant:i64<3>, Constant:i64<4>, Constant:i64<5>, Constant:i64<6>, Constant:i64<7> t16: v8i64 = add t7, t15 t18: ch = CopyToReg t0, Register:v8...
2018 Apr 09
2
A way to opt out of a dag combine?
...DAG describes building a v2f16 vector from elements [0, 2]. The combine translates this to building a vector from elements [0, 0]. The problem seems to be treating extract_subvector with different constants as instances of the same value. t14: v2f16 = extract_subvector t2, Constant:i32<2> t15: f16 = extract_vector_elt t14, Constant:i32<0> t16: v2f16 = extract_subvector t2, Constant:i32<0> t17: f16 = extract_vector_elt t16, Constant:i32<0> t9: v2f16 = BUILD_VECTOR t17, t15 ... into: t19: v2f16 = vector_shuffle<0,0> t16, undef:v2f16 // fail ---------...
2016 Sep 03
4
llc error
...s, LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17 t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16, undef:i64 t16: i64 = add t2, Constant:i64<16> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5 t1: i64 = Register %vreg5 t15: i64 = Constant<16> t4: i64 = undef In function: _ZN10soundtouch12TDStretchSSE13calcCrossCorrEPKfS2_Rd I dug into the LLVM assembly file and found out that the error is caused by the following 2 lines (Line 89 and 90). %8 = shufflevector <4 x float> %6, <4 x float> %6, <...