Displaying 9 results from an estimated 9 matches for "t128".
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2016 Jun 25
2
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
I have a problem with VectorLegalizer::ExpandStore() with v4i1.
Let's see a example.
* LLVM IR
store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
* SelectionDAG before vector legalization
ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
* SelectionDAG after vector legalization
ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32, undef:i64
t133: i32 = extract_vector_elt t128, Constant:i64<0>
ch = store<ST1[%16](align=4), trunc to i1> t0, t136, t32, undef:i64
t136: i32 = extract_vector_elt...
2016 Jun 28
0
Question about VectorLegalizer::ExpandStore() with v4i1
...have a problem with VectorLegalizer::ExpandStore() with v4i1.
>
> Let's see a example.
>
> * LLVM IR
> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>
> * SelectionDAG before vector legalization
> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
>
> * SelectionDAG after vector legalization
> ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32, undef:i64
> t133: i32 = extract_vector_elt t128, Constant:i64<0>
> ch = store<ST1[%16](align=4), trunc to i1> t0, t136, t32, undef:i64
> t...
2016 Jun 28
2
Question about VectorLegalizer::ExpandStore() with v4i1
...izer::ExpandStore() with v4i1.
>>
>> Let's see a example.
>>
>> * LLVM IR
>> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>>
>> * SelectionDAG before vector legalization
>> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
>>
>> * SelectionDAG after vector legalization
>> ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32, undef:i64
>> t133: i32 = extract_vector_elt t128, Constant:i64<0>
>> ch = store<ST1[%16](align=4), trunc to i1> t0, t136, t32...
2012 Feb 22
2
[LLVMdev] Eliminating copies between overlapping register classes
Hi,
I have two register classes A and B, where A contains a subset of the
registers in B:
A = [R0, R1, R2, ... R128]
B = [RO, R1, R2, ... R128,
T0, T1, T2, ... T128]
I am using the Greedy Register Allocator, and I would expect the register
allocator to eliminate this copy:
%vreg0<def> = COPY %vreg1; B:%vreg0 A:%vreg1
but instead I end up with
%R0<def> = COPY %R1
Is there any way I can get the register allocator to eliminate these
kinds of copi...
2012 Feb 23
0
[LLVMdev] Eliminating copies between overlapping register classes
On Feb 22, 2012, at 12:01 PM, Tom Stellard wrote:
> Hi,
>
> I have two register classes A and B, where A contains a subset of the
> registers in B:
>
> A = [R0, R1, R2, ... R128]
>
> B = [RO, R1, R2, ... R128,
> T0, T1, T2, ... T128]
>
> I am using the Greedy Register Allocator, and I would expect the register
> allocator to eliminate this copy:
>
> %vreg0<def> = COPY %vreg1; B:%vreg0 A:%vreg1
>
> but instead I end up with
>
> %R0<def> = COPY %R1
>
> Is there any way I can get...
2012 Feb 23
1
[LLVMdev] Eliminating copies between overlapping register classes
...12, at 12:01 PM, Tom Stellard wrote:
>
> > Hi,
> >
> > I have two register classes A and B, where A contains a subset of the
> > registers in B:
> >
> > A = [R0, R1, R2, ... R128]
> >
> > B = [RO, R1, R2, ... R128,
> > T0, T1, T2, ... T128]
> >
> > I am using the Greedy Register Allocator, and I would expect the register
> > allocator to eliminate this copy:
> >
> > %vreg0<def> = COPY %vreg1; B:%vreg0 A:%vreg1
> >
> > but instead I end up with
> >
> > %R0<def> = CO...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...undef:i64, undef:i64, undef:i64...
Split node result: t126: v8i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64...
Split node result: t127: v4i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64...
Split node result: t128: v2i64 = BUILD_VECTOR undef:i64, undef:i64
Split node operand: t122: v128i16,ch = masked_gather<LD128[<unknown>](align=256)> t0,
t130, t193, TargetConstant:i64<0>, t121
llc:
/home/asusu/LLVM/llvm38Nov2016/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6804:
llvm::Me...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...4, undef:i64...
> Split node result: t126: v8i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64...
> Split node result: t127: v4i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> undef:i64...
> Split node result: t128: v2i64 = BUILD_VECTOR undef:i64, undef:i64
>
> Split node operand: t122: v128i16,ch = masked_gather<LD128[<unknown>](align=256)> t0,
> t130, t193, TargetConstant:i64<0>, t121
>
> llc:
> /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6804:
> llvm::MemS...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure: