Displaying 20 results from an estimated 76 matches for "t12".
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2016 Nov 03
2
rotl: undocumented LLVM instruction?
...EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>>
>> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>>
&...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9...
2009 Sep 29
1
How to parsing data like this in R
Hi, R-users,
I met a problem:
Items:[Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t16\t00\t00\t11]/Anne 'Ei jakoa,uus päivä muistio et 4n niin peruin. Hups'\t (0:16)\t0\t12\t18\t00\t00\t11/Elina 'Konsertissa. En tod. vastaa teille'\tEtu-Töölö, Helsinki (2:40)\t24\t12\t18\t00\t00\t11
I want to parsing the above data into the below according to each "/"...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...,ch = CopyFromReg t0, Register:i64 %vreg1
> t6: i64 = sub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>
>
> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
&g...
2016 Jun 22
2
LLVM Backend Issues
...T4[%retval]> t0, Constant:i32<0>,
FrameIndex:i32<0>, undef:i32
t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>,
undef:i32
t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>,
FrameIndex:i32<3>, undef:i32
t12: ch = store<ST4[%m]> t10, Constant:i32<0>, FrameIndex:i32<19>,
undef:i32
t13: i32,ch = load<LD4[%sz]> t12, FrameIndex:i32<2>, undef:i32
t15: ch = store<ST4[%j]> t13:1, t13, FrameIndex:i32<16>, undef:i32
t17: ch = store<ST4[%le]> t15, t13, Fram...
2008 Feb 11
3
Difference between P.Value and adj.P.Value
Hallo,
> fit12<-lmFit(qrg[,1:2])
> t12<-toptable(fit12,adjust="fdr",number=25,genelist=qrg$genes[,1])
> t12
ID logFC t P.Value adj.P.Val B
522 PLAU_OP -6.836144 -8.420414 5.589416e-05 0.01212520 2.054965
1555 CD44_WIZ -6.569622 -8.227938 6.510169e-05...
2007 Mar 01
2
[LLVMdev] Version 1.9 SSA form question
...%.t4 = or uint %.t3, %param.x ; <uint> [#uses=2]
%.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1]
%.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2]
%.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1]
%.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2]
%.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1]
%.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2]
%.t19 = shr uint %.t16, ubyte 16 ; <uint>
[#uses=1]
%.t20...
2010 Jul 28
2
Ghostcast random freeze.
...elinux since it basically is loading a Linux kernel then booting a MSDos.imz file. I cannot find any errors from the ghostcast side or the ghost error file.
Here is the pxelinux menu item I am choosing which I created.
# MS-DOS Loader for GHOST Cast Server
LABEL GHOST
MENU DEFAULT
MENU LABEL ^1. T12 Group 1 Session 1
KERNEL MEMDISK
append initrd=imz/t12/T12-G1-1.imz stack=4096 raw keeppxe
I have added the Stack, Raw, and keeppxe settings while trying to diagnose if there was a memory issue with how the imz is loaded up.
Inside the imz file the only important line to mention is the ghost line...
2008 Jan 24
3
store variable as tab-del. txt-file
Hallo,
how can I store a variable as a tab-delimited txt-file? I crated a
variable with the following commands:
> fit12<-lmFit(qrg[,1:2])
> t12<-toptable(fit12,adjust="fdr",number=25,genelist=qrg$genes[,1])
> t12
ID logFC t P.Value adj.P.Val B
522 PLAU_OP -6.836144 -8.420414 5.589416e-05 0.01212520 2.054965
1555 CD44_WIZ -6.569622 -8.227938 6.510169e-05...
2016 Jun 21
3
LLVM Backend Issues
Hi,
I am having issues running a new backend that I created for a new
architecture. I suspect these errors may have something to do with how I
have the string setup in LLVMTargetMachine() below?
Also - It would be great if someone could point me to a document that
describes some of these error messages? For example what does t26 ..t4 mean?
Thanks in advance for taking your valuable time to help
2024 Jan 29
1
linear programming in R | limits to what it can do, or my mistake?
...cient matrix (typically, the LHS) since each line of said
matrix, which corresponds to the constraints, needs to be a function of
the unknowns in the objective function -- being, p1, p2, p3 and p4.
In Maple (for example), this is trivial:
???? cost:=35*p10+55*p12+50*p14+65*p16;
cnsts:={t10=640,t12=t10-p10+825,t14=t12-p12+580,t16=t14-p14+925,t16-p16=0,p10<=t10,p12<=t12,p14<=t14,p16<=t16,t10<=1000,t12<=1000,t14<=1000,t16<=1000};
? ?? Minimize(cost,cnsts,assume={nonnegative});
which yields (correctly):
p1=640, p2=405, p3=1000, p4=925
for minimized cost of 154800.
To...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...s 36 nodes:
t0: ch = EntryToken
t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
t4: i32 = or t2, Constant:i32<256>
t9: i32 = shl t4, Constant:i32<2>
t10: i32 = add t6, t9
t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
t16: ch = llvm.tpu.dma.write.1KB.async t0,
TargetConstant:i32<4602>, t10, t12, t15
t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
t20: i32 = AssertZext...
2024 Jan 30
1
linear programming in R | limits to what it can do, or my mistake?
...since each line of said
> matrix, which corresponds to the constraints, needs to be a function of
> the unknowns in the objective function -- being, p1, p2, p3 and p4.
>
> In Maple (for example), this is trivial:
>
> ???? cost:=35*p10+55*p12+50*p14+65*p16;
> cnsts:={t10=640,t12=t10-p10+825,t14=t12-p12+580,t16=t14-p14+925,t16-p16=0,p10<=t10,p12<=t12,p14<=t14,p16<=t16,t10<=1000,t12<=1000,t14<=1000,t16<=1000};
> ? ?? Minimize(cost,cnsts,assume={nonnegative});
>
> which yields (correctly):
>
> p1=640, p2=405, p3=1000, p4=925
>
&g...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
>> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
>> t4: i32 = or t2, Constant:i32<256>
>> t9: i32 = shl t4, Constant:i32<2>
>> t10: i32 = add t6, t9
>> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
>> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
>> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15
>> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
>&g...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...e
> command -view-dag-combine2-dags i get the required output in graph
> but the following error on console:
>
> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x
> i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7,
> t12, undef:i64
> t7: v64i32 = add t6, t4
> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14,
> undef:i64
> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[6...
2012 Aug 29
4
Sorting of columns of a matrix
Dear all,
Please suggest me how can I do it.
I have a matrix which look like following:
x1 x2 x3 t1 .01 0.3 0 t2 0 0.1 0.01 t3 0 .01 .01 t4 0 0 t5 5 0 0 t6
0 0 0 t7 0 0 0 t8 0 0 0 t9 0.6 0 0 t10 0 0 0.66 t11 0 0.6 0.11 t12 0
0.4 0
I want to sort decreasing order in each column based on rows. and then to
display only those rows which has a value. The expected out put matrix will
look like
x1 x2 x3 t9 0.6 t11 0.6 t10 0.66 t1 .01 t12 0.4 t11 0.11 t1 0.3 t2 .01
t2 0.1 t3 .01
many thanks
Nico
[[alternative H...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...when i use the command -view-dag-combine2-dags i
>> get the required output in graph but the following error on console:
>>
>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a
>> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>> t7: v64i32 = add t6, t4
>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]*...
2019 Jun 05
2
Strange behaviour of post-legalising optimisations(?)
...ng constant: t6: i16 = Constant<0>
Creating new node: t7: i16 = undef
Creating new node: t8: i8,ch = load<(load 1 from %ir.scevgep1, !tbaa !2)> t0, t5, undef:i16
Creating new node: t10: i16,ch = CopyFromReg t0, Register:i16 %2
Creating new node: t11: i16 = add t10, t4
Creating new node: t12: ch = store<(store 1 into %ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16
Creating constant: t13: i16 = Constant<1>
Creating new node: t14: i16 = add nuw nsw t4, Constant:i16<1>
Creating new node: t16: ch = CopyToReg t0, Register:i16 %1, t14
Creating new node: t17: ch = TokenFact...
2017 Jul 06
2
Error in v64i32 type in x86 backend
...owering.cpp.
and rebuild llvm. then when i use the command -view-dag-combine2-dags i get
the required output in graph but the following error on console:
LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a to
<64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
t7: v64i32 = add t6, t4
t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0
t13: i64 = TargetG...