search for: src1

...efine OP00_LBL(op) define op(label) ureg_##op(ureg, label) +#define OP01_LBL(op) define op(src, label) ureg_##op(ureg, _src(src), label) +#define OP10(op) define op(dst) ureg_##op(ureg, dst) +#define OP11(op) define op(dst, src) ureg_##op(ureg, dst, _src(src)) +#define OP12(op) define op(dst, src0, src1) ureg_##op(ureg, dst, _src(src0), _src(src1)) +#define OP12_TEX(op) define op(dst, target, src0, src1) ureg_##op(ureg, dst, TGSI_TEXTURE_ CAT target, _src(src0), _src(src1)) +#define OP13(op) define op(dst, src0, src1, src2) ureg_##op(ureg, dst, _src(src0), _src(src1), _src(src2)) +#define OP14_TEX...

...[]>; >> >> let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in >> -def POST_LDrid : LDInstPI<(outs DoubleRegs:$dst, IntRegs:$dst2), >> +def POST_LDrid : LDInst2PI<(outs DoubleRegs:$dst, IntRegs:$dst2), >> (ins IntRegs:$src1, s4Imm:$offset), >> "$dst = memd($src1++#$offset)", >> [], >> @@ -895,64 +895,64 @@ def POST_LDrid : LDInstPI<(outs DoubleRegs:$dst, IntRegs:$dst2), >> >> // Load doubleword conditionally. >> let mayLoad = 1, neverHasS...

...====== > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu May 26 18:13:19 2011 > @@ -4935,66 +4935,66 @@ > // This set of instructions are only rm, the only difference is the size > // of r and m. > let Constraints = "$src1 = $dst" in { > - def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst), > + def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst), > (ins GR32:$src1, i8mem:$src2), > "crc32{b} \t{$src2, $src1|$src1, $src2}", >...

Currently, instruction selection patterns are defined like this: def : Pat<(and (not GR32:$src1), GR32:$src2), (ANDN32rr GR32:$src1, GR32:$src2)>; def : Pat<(and (not GR64:$src1), GR64:$src2), (ANDN64rr GR64:$src1, GR64:$src2)>; TableGen infers the types of $src1 and $src2 from the specified register classes, and that is the only purpose of the register cl...

...but sometimes if a vector_shuffle can only return LHS or RHS, it's removed/combined so that I cannot match vector_shuffle in the instruction selector. If the vector_shuffle is combined, I have to write the instruction selector like these: def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1), [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0), (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)] def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1), [sub REG:$src0, (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]...

...llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu > Sent: Thursday, March 21, 2013 1:26:25 PM > Subject: [LLVMdev] Simpler types in TableGen isel patterns > > Currently, instruction selection patterns are defined like this: > > def : Pat<(and (not GR32:$src1), GR32:$src2), > (ANDN32rr GR32:$src1, GR32:$src2)>; > def : Pat<(and (not GR64:$src1), GR64:$src2), > (ANDN64rr GR64:$src1, GR64:$src2)>; > > TableGen infers the types of $src1 and $src2 from the specified > register classes, and that is the o...

...;, "") I define the intrinsic as Pseudo instruction,it succeed. But when mapping a new instruction.I don't know how to do. In x86InstrArithmetic.td. I add ,(To make sure the Sched is right, I use the WriteIMul16Reg ) def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32 ; when compile LLVM , the error appears. "[ 97%] Updating X86GenAsmWriter1.inc... Unhandled immediate encoding GR32 Unhandled immediate enco...

Thank You. But can we use same register class for fadd as well, is this instruction correct? def VFADD : I<0x0E, MRMDestReg, (outs VRR128:$dst), (ins VRR128:$src1, VRR128:$src2),"VFADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRR128:$dst, (fadd VRR128:$src1, VRR128:$src2))]>, TA; On Tue, Jul 11, 2017 at 9:00 PM, Craig Topper <craig.topper at gmail.com> wrote: > "add" only works for integers. Floating point requires f...

...8-bit versions too? I added the avx checks to the same file (in which case calling it sse3-haddsub.ll is not so great). > 4) Your tablegen modifications are totally fine, for the intrinsics just do: > > let Predicates = [HasSSE3] in { > def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), VR128:$src2), > (HADDPSrr VR128:$src1, VR128:$src2)>; > def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), (memop addr:$src2)), > (HADDPSrm VR128:$src1, addr:$src2)>; > ... > > and > > let Predicates = [HasAVX] in { > def : Pat<(int_x...

...], [llvm_i16_ty, llvm_i16_ty], [IntrNoMem]>; that I want to translate to the following instruction during instruction selection: def divm16_pseudo : MyPseudoInst< (outs aNh_0_7:$dst, aNh_0_7:$dst2), (ins aNh_0_7:$src1, aNh_0_7:$src2)>; So I've done a pattern the same way I've done for numerous other intrinsics (that returns simple types like i16/i32 etc): def : Pat<(int_phx_divm_u16 i16:$src1, i16:$src2), (divm16_pseudo $src1, $src2)>; But this doesn't work for me: anonymous_...

Bill, Sorry if I wasn't clear enough. I wasn't referring to multiclass's that define other classes, but with using patterns inside of a multiclass to reduce redundant code. For example: multiclass IntSubtract<SDNode node> { def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1), (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>; } or something similar. I just want to write the pattern once and then have it apply to multiple registe...

Hi, I have a simple question w.r.t the order of operands used in dag pattern matching in target files. Some of them seem intuitive. But I want to get it clarified anyway. I am using a pattern from X86InstrFMA.td in the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, ValueType OpVT, PatFrag mem_frag, SDPatternOperator OpNode = null_frag> { def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),...

...n; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> { def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>; def _i16 : BinaryOp<OpCode, OpN...

...wasn't clear enough. I wasn't referring to multiclass's that > define other classes, but with using patterns inside of a multiclass to > reduce redundant code. > For example: > multiclass IntSubtract<SDNode node> > { > def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), > (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; > def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1), > (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>; > } > > or something similar. > I just want to write the pattern once and then ha...

...[llvm_i16_ty, llvm_i16_ty], > [IntrNoMem]>; > > that I want to translate to the following instruction during instruction selection: > > def divm16_pseudo : MyPseudoInst< > (outs aNh_0_7:$dst, aNh_0_7:$dst2), > (ins aNh_0_7:$src1, aNh_0_7:$src2)>; > > So I've done a pattern the same way I've done for numerous other intrinsics (that returns simple types like i16/i32 etc): > > def : Pat<(int_phx_divm_u16 i16:$src1, i16:$src2), > (divm16_pseudo $src1, $src2)>; It isn’t able to infer...

...%sub = sub nsw i32 %0, 1 ret i32 %sub } But finally in code generation i am getting: ldc r2, #-1 add r0, r2, r0 Should this not be doing: ldc r2 #1 sub r0 r2 r0 I have defined both my add and sub instructions: def ADD : ALUInst<0b0001, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "add $src1, $src2, $dst", [(set i32:$dst, (add i32:$src1, i32:$src2))]>; def SUB : ALUInst<0b0010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "sub $src1, $src2, $dst",...

...16_ty], >> [IntrNoMem]>; >> >> that I want to translate to the following instruction during instruction selection: >> >> def divm16_pseudo : MyPseudoInst< >> (outs aNh_0_7:$dst, aNh_0_7:$dst2), >> (ins aNh_0_7:$src1, aNh_0_7:$src2)>; >> >> So I've done a pattern the same way I've done for numerous other intrinsics (that returns simple types like i16/i32 etc): >> >> def : Pat<(int_phx_divm_u16 i16:$src1, i16:$src2), >> (divm16_pseudo $src1, $src2)>; >...

Thank You. How to do the same for add please see the following; it gives duplication error. def VADD : I<0x0E, MRMDestReg, (outs VRR128:$dst), (ins VRR128:$src1, VRR128:$src2),"VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRR128:$dst, (add VRR128:$src1, VRR128:$src2))]>, TA; def : Pat<(add VRR128:$src1, VRR128:$src2), (VADD VRPIM128:$src1, VRPIM128:$src2)>; Where to place v32f32 to distinguish between the two? On Tue, Jul 11...

...le, I want to be able to do this: > > defm MOVH : > vs1x_fps_binary_vv_node_rmonly< > 0x16, "movh", undef, 0, > // rr > [(undef)], > // rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DSTTYPE (bitconvert > (v2f64 (scalar_to_vector > (loadf64 addr:$src2))))))))], > // rr Pat > [], > // rm Pat >...

...2=162998&pathrev=162999 For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>; ... It seems that previous revisions for fma4 intrinsics also followed...