search for: sutter

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2012 Mar 06
2
[LLVMdev] Recent changes to MCRegisterClass fields: uint8_t is too narrow
...available registers of any type in a machine description is decreased to 256 because it needs to be encoded in uint8_t now. I'm trying to support an experimental embedded architecture with more registers (out of tree), but now that becomes impossible. Anyone knows a solution? Thanks, Bjorn De Sutter Computer Systems Lab Ghent University
2011 Nov 14
2
[LLVMdev] alias analysis in ScheduleDagInstr class
...is the exact nature of > your question? > > Sergei Larin > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Bjorn De Sutter > Sent: Friday, November 11, 2011 7:59 AM > To: llvmdev at cs.uiuc.edu > Subject: [LLVMdev] alias analysis in ScheduleDagInstr class > > In ScheduleDagInstr.cpp, a todo is mentioned to make this pass use real > alias analysis information. Is anybody working on this already? >...
2011 Nov 11
2
[LLVMdev] alias analysis in ScheduleDagInstr class
...his pass use real alias analysis information. Is anybody working on this already? I am working on a VLIW-like backend and have If-conversion working rather well, but the problem is that independent loads and stores in the if-converted blocks are not scheduled well at all. Thanks, prof. Bjorn De Sutter Computer Systems Lab Ghent University
2011 Nov 14
0
[LLVMdev] alias analysis in ScheduleDagInstr class
...nted at the same time. What is your timeline? How much time you can afford until you must have this? Also, are you attending the LLVM meeting in San Jose this week? Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -----Original Message----- From: Bjorn De Sutter [mailto:bjorn.desutter at elis.ugent.be] Sent: Monday, November 14, 2011 10:18 AM To: Sergei Larin Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] alias analysis in ScheduleDagInstr class Hi Sergei, thanks for considering my question. We if-convert some code, such that the basic block looks as...
2012 Mar 06
0
[LLVMdev] Recent changes to MCRegisterClass fields: uint8_t is too narrow
I changed it to uint16_t in r152100. Is that enough for your architecture? On Tue, Mar 6, 2012 at 12:24 AM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > Hi all, > > in r152019 (from ctopper), the number of available registers of any type > in a machine description is decreased to 256 because it needs to be encoded > in uint8_t now. I'm trying to support an experimental embedded a...
2011 Nov 14
0
[LLVMdev] alias analysis in ScheduleDagInstr class
...am working on something very(very) similar, what is the exact nature of your question? Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Bjorn De Sutter Sent: Friday, November 11, 2011 7:59 AM To: llvmdev at cs.uiuc.edu Subject: [LLVMdev] alias analysis in ScheduleDagInstr class In ScheduleDagInstr.cpp, a todo is mentioned to make this pass use real alias analysis information. Is anybody working on this already? I am working on a VLIW-like backen...
2012 Nov 27
2
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
...upon your post. > I observed similar behaviour whenever I did not include > > #include "llvm/Support/Debug.h" > #include "llvm/Support/raw_ostream.h" > > I'm working on release 3.1 though. > > hth, Daniel > > On 11/26/2012 03:00 PM, Bjorn De Sutter wrote: >> Hi, >> >> I am trying to debug my backend, and observe very strange behavior with dbgs(): >> >> In the IfConverter, I have added two debugging lines that print floating-point numbers for the sake of demonstration that such printing works fine. >> &gt...
2020 Nov 05
3
[Bug 1479] New: seqnum_to_json() is slow
https://bugzilla.netfilter.org/show_bug.cgi?id=1479 Bug ID: 1479 Summary: seqnum_to_json() is slow Product: nftables Version: unspecified Hardware: All OS: All Status: NEW Severity: enhancement Priority: P5 Component: nft Assignee: pablo at netfilter.org Reporter:
2024 Jan 29
2
[Bug 1734] New: nft set with auto-merge json import/export
https://bugzilla.netfilter.org/show_bug.cgi?id=1734 Bug ID: 1734 Summary: nft set with auto-merge json import/export Product: nftables Version: 1.0.x Hardware: All OS: All Status: NEW Severity: minor Priority: P5 Component: nft Assignee: pablo at netfilter.org
2003 Nov 04
2
4-STABLE b0rked in share/locale/zh_CN.GBK
...GB18030.out /usr/share/locale/zh_CN.GB18030/LC_CTYPE install -m 644 -o root -g wheel zh_CN.GBK.out /usr/share/locale/zh_CN.GBK/LC_CTYPE install: /usr/share/locale/zh_CN.GBK/LC_CTYPE: No such file or directory *** Error code 71 Stop in /usr/src/share/mklocale. *** Error code 1 Greg -- Gregory S. Sutter Build a man a fire, and he'll be warm mailto:gsutter@zer0.org for a day. Set a man on fire, and he'll http://zer0.org/~gsutter/ be warm for the rest of his life. -------------- next part -------------- A non-text attachment was scrubbed... Name: not...
2012 Oct 31
3
[LLVMdev] : Predication on SIMD architectures and LLVM
...iation interval constraints (such as ResMII, RecMII). In my view, the ideal would be to have very generic, full (OpenIMPACT-like) predication support throughout LLVM, with the option of enabling/skipping early if-conversion just like one can enable or disable aggressive inlining. Best, Bjorn De Sutter Computer Systems Lab Ghent University
2023 Dec 18
4
[Bug 1728] New: Regression: iptables lock is now waited for without --wait
https://bugzilla.netfilter.org/show_bug.cgi?id=1728 Bug ID: 1728 Summary: Regression: iptables lock is now waited for without --wait Product: iptables Version: 1.8.x Hardware: x86_64 OS: All Status: NEW Severity: normal Priority: P5 Component: unknown
2012 Nov 27
0
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
Can you try making the constructor "explicit" for PrintReg in include/llvm/Target/TargetRegisterInfo.h. I think you were getting an implicit conversion there which should probably be fixed anyway. On Mon, Nov 26, 2012 at 11:47 PM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > Hi, > > that solved my problem on trunk as well, thanks. Strange that you have to > include this though. > > Bjorn > > On 27 Nov 2012, at 00:00, Daniel Prokesch <daniel.prokesch at gmail.com> > wrote: > > >...
2020 Jan 06
9
[Bug 1395] New: Add element fails with Error: Could not process rule: Invalid argument
https://bugzilla.netfilter.org/show_bug.cgi?id=1395 Bug ID: 1395 Summary: Add element fails with Error: Could not process rule: Invalid argument Product: nftables Version: unspecified Hardware: All OS: All Status: NEW Severity: critical Priority: P5 Component: nft
2017 Apr 02
6
[Bug 1142] New: invalid binop operation 6nft
https://bugzilla.netfilter.org/show_bug.cgi?id=1142 Bug ID: 1142 Summary: invalid binop operation 6nft Product: nftables Version: unspecified Hardware: x86_64 OS: other Status: NEW Severity: major Priority: P5 Component: nft Assignee: pablo at netfilter.org Reporter:
2012 Nov 27
1
[LLVMdev] strange dbgs() behavior: unable to print floats in machine backend
...g.topper at gmail.com> wrote: > Can you try making the constructor "explicit" for PrintReg in include/llvm/Target/TargetRegisterInfo.h. I think you were getting an implicit conversion there which should probably be fixed anyway. > > On Mon, Nov 26, 2012 at 11:47 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > Hi, > > that solved my problem on trunk as well, thanks. Strange that you have to include this though. > > Bjorn > > On 27 Nov 2012, at 00:00, Daniel Prokesch <daniel.prokesch at gmail.com> wrote: > > > Hi, &gt...
2012 Nov 01
0
[LLVMdev] : Predication on SIMD architectures and LLVM
On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested con...
2015 Jan 21
2
question about installing samba and writing VFS module...
On 1/21/2015 11:49 AM, Rowland Penny wrote: > On 21/01/15 15:40, Ed Sutter wrote: >> On 1/21/2015 10:18 AM, Rowland Penny wrote: >>> On 21/01/15 15:05, Ed Sutter wrote: >>>> Hi, >>>> I'm new to Samba. My goal is to write a VFS module. >>>> I've been able to do this somewhat successfully; however there must be a b...
2015 Jan 26
1
how to add new vfs module to build...
On 1/24/2015 3:03 PM, Volker Lendecke wrote: > On Sat, Jan 24, 2015 at 01:35:40PM -0500, Ed Sutter wrote: >> Hi, >> I'm working with version 4.1.6 to create a new VFS module. >> I've been experimenting by just modifying one of the existing >> module source files (vfs_full_audit.c) and that rebuilds as expected. >> >> I want to step back now and create...
2008 Mar 10
1
(no subject)
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