Displaying 8 results from an estimated 8 matches for "supperreg".
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2008 Oct 02
2
[LLVMdev] INSERT_SUBREG node.
What's the value produced by an INSERT_SUBREG node? Is it a chain?
Can I use to set a superreg of i16 type with two i8 values, and use the
supperreg as an operand somewhere else?
- Sanjiv
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2008 Oct 02
0
[LLVMdev] INSERT_SUBREG node.
...e produced by an INSERT_SUBREG node? Is it a chain?
No, insert_subreg returns a value:
v1 = insert_subreg v2, v3, idx
v1 and v2 will have the same type, e.g. i16, and v3 must have a sub-
register type, e.g. i8.
> Can I use to set a superreg of i16 type with two i8 values, and use
> the supperreg as an operand somewhere else?
Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The
way to do it is:
v4 = insert_subreg implicit_def, v1, 0
v3 = insert_subreg v4, v2, 1
Evan
>
> - Sanjiv
> _______________________________________________
> LLVM Develop...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...sert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
> sub-register type, e.g. i8.
>
> >
> > Can I use to set a superreg of i16 type with two i8 values, and use
> > the supperreg as an operand somewhere else?
>
>
> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The
> way to do it is:
>
>
> v4 = insert_subreg implicit_def, v1, 0
> v3 = insert_subreg v4, v2, 1
>
>
> Evan
>
This is how my register cla...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...t;
>>
>> v1 = insert_subreg v2, v3, idx
>>
>>
>> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>> sub-register type, e.g. i8.
>>
>>>
>>> Can I use to set a superreg of i16 type with two i8 values, and use
>>> the supperreg as an operand somewhere else?
>>
>>
>> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The
>> way to do it is:
>>
>>
>> v4 = insert_subreg implicit_def, v1, 0
>> v3 = insert_subreg v4, v2, 1
>>
>>
>> E...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...v2, v3, idx
> >>
> >>
> >> v1 and v2 will have the same type, e.g. i16, and v3 must have a
> >> sub-register type, e.g. i8.
> >>
> >>>
> >>> Can I use to set a superreg of i16 type with two i8 values, and use
> >>> the supperreg as an operand somewhere else?
> >>
> >>
> >> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The
> >> way to do it is:
> >>
> >>
> >> v4 = insert_subreg implicit_def, v1, 0
> >> v3 = insert_subreg v4,...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...gt;>>> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>>>> sub-register type, e.g. i8.
>>>>
>>>>>
>>>>> Can I use to set a superreg of i16 type with two i8 values, and
>>>>> use
>>>>> the supperreg as an operand somewhere else?
>>>>
>>>>
>>>> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The
>>>> way to do it is:
>>>>
>>>>
>>>> v4 = insert_subreg implicit_def, v1, 0
>>>> v3 = inse...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...have the same type, e.g. i16, and v3 must have a
> >>>> sub-register type, e.g. i8.
> >>>>
> >>>>>
> >>>>> Can I use to set a superreg of i16 type with two i8 values, and
> >>>>> use
> >>>>> the supperreg as an operand somewhere else?
> >>>>
> >>>>
> >>>> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The
> >>>> way to do it is:
> >>>>
> >>>>
> >>>> v4 = insert_subreg implicit_de...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...ype, e.g. i16, and v3 must have a
>>>>>> sub-register type, e.g. i8.
>>>>>>
>>>>>>>
>>>>>>> Can I use to set a superreg of i16 type with two i8 values, and
>>>>>>> use
>>>>>>> the supperreg as an operand somewhere else?
>>>>>>
>>>>>>
>>>>>> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3.
>>>>>> The
>>>>>> way to do it is:
>>>>>>
>>>>>>
>>...