search for: subtargets

Displaying 20 results from an estimated 637 matches for "subtargets".

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2015 Apr 09
2
[LLVMdev] MMX/SSE subtarget feature in IR
Hi all, I have a sample test case : $ cat 1.c int foo(int x, int y){ int z = x + y; return z/2; } I tried to get its IR form with clang providing subtarget feature as mmx for target x86_64 $ clang -O3 -mmmx 1.c -S -emit-llvm in the IR generated i can see the subtarget-features as function attribute : "target-features"="+mmx" In the SelectionDAG phase in file
2017 Aug 22
2
Subtarget Initialization in <ARCH>TargetMachine constructor
Hi, I found some different discrepancy on how Subtarget is created between some arch specific TargetMachine constructor. For example, for BPF/Lanai: BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options,
2017 Oct 17
2
getCacheSize() / subtarget machine id
Hi, while implementing SystemZTTI:getCacheSize(), it became clear that there really isn't a simple way to just ask the Subtarget for the current subtarget machine model. I was thinking like something of an enum that would also reflect the subtarget series (and would allow >= and similar operations). I would like to ask what the ideas are on how this should be done best. Some
2016 Feb 21
2
Schedule pass for a subtarget?
[resending to correct llvm-dev address] Hi, I’d like to start enabling the loop data prefetch pass for Cyclone (an ARM64 subtarget). AFAICT, you can’t really add passes specifically to a subtarget but only to a target. This makes sense because in the new world, you could have different subtargets per function. I just want to make sure my understanding is correct. My plan is to add the pass for the target and then exit the pass early based on a TTI hook (getPrefetchDistance is not set). Currently, PowerPC gets around this problem by checking the vendor part of the triple to decide whether...
2019 Mar 13
2
Per-function subtargets
I've been trying to understand the current state of subtargets and subtarget features in LLVM. It seems like the presence of "target-cpu" and "target-features" attributes on IR functions are currently intended to take precedence over the module-level (TargetMachine) versions. See X86TargetMachine::getSubtargetImpl for an example of this...
2013 Nov 26
4
[LLVMdev] [RFC] CGContext skeleton implementation
...g up on the "CodeGen Context" discussion that was started, attached is patch which implements a pretty minimal skeleton of a CGContext implementation. The goal is to allow the newly added subtarget attributes on functions to be made available to codegen so that codegen can actually switch subtargets within a Module. Comments and questions are invited herewith. There has been some disagreement as to what to name this class. I have stuck with "CGContext" for now, though I'm absolutely not attached to that name. It demonstrates where the CGContext state lives, how code can access...
2013 Dec 05
4
[LLVMdev] [RFC] CGContext skeleton implementation
...deGen Context" discussion that was started, > attached is patch which implements a pretty minimal skeleton of a CGContext > implementation. The goal is to allow the newly added subtarget attributes > on functions to be made available to codegen so that codegen can actually > switch subtargets within a Module. > > > > Comments and questions are invited herewith. > > > > There has been some disagreement as to what to name this class. I have > stuck with "CGContext" for now, though I'm absolutely not attached to that > name. > > > > I...
2015 Jan 27
7
[LLVMdev] Embedding cpu and feature strings into IR and enabling switching subtarget on a per function basis
I've been investigating what is needed to ensure command line options are passed to the backend codegen passes during LTO and enable compiling different functions in a module with different command line options (see the links below for previous discussions). http://thread.gmane.org/gmane.comp.compilers.llvm.devel/78855 http://thread.gmane.org/gmane.comp.compilers.llvm.devel/80456 The command
2017 Aug 23
2
Subtarget Initialization in <ARCH>TargetMachine constructor
...btargetImpl() tries to >> get the value >> from SubtargetMap. >> >> Is there any downside to keep BPFTargetMachine as is? Or it is worthwhile to >> implement it in a similar way to X86/ARM? > > My understanding is that SubtargetMap is used to allow different > subtargets to be returned for different functions/modules based on > attributes (e.g. one function might be soft-float, another function > might have a particular feature string or CPU in its attributes. I've > CCed in Eric Christopher who worked on this and can hopefully clarify > or correct...
2013 Dec 03
0
[LLVMdev] [RFC] CGContext skeleton implementation
...g up on the "CodeGen Context" discussion that was started, attached is patch which implements a pretty minimal skeleton of a CGContext implementation. The goal is to allow the newly added subtarget attributes on functions to be made available to codegen so that codegen can actually switch subtargets within a Module. > > Comments and questions are invited herewith. > > There has been some disagreement as to what to name this class. I have stuck with "CGContext" for now, though I'm absolutely not attached to that name. > > It demonstrates where the CGContext st...
2015 Apr 09
2
[LLVMdev] MMX/SSE subtarget feature in IR
Thanks Kevin for the reply. I got the point now :) On 10 Apr 2015 00:18, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote: > For x86_64 ABI, a minimum feature set of SSE2 is required. > > > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09,
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
Please tell me whether the following implementation is correct..... My target supports 64 bit mask means immediate(0-2^63) I have implemented it but i dont know whether its correct or not. Please see the changes below that i have made in x86isellowering.cpp static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
2020 Nov 10
1
Fwd: Select output section for a function based on a subtarget feature
...'m enabling this feature for appropriate CPUs. Now, functions that are compiled with "vle" feature should go into a different text section (text_vle). I can see that TargetMachine has a method getSubtargetImpl which can be overridden for the implementation and it can return different subtargets for different function attributes. What I'm struggling with is connecting it to section selection; in MCObjectFileInfo::initELFMCObjectFileInfo a default text section is created but since here section should be selected based on function, I'm not sure where object file writer implementation...
2017 Mar 29
3
clang 4.0.0: Invalid code for builtin floating point function with -mfloat-abi=hard -ffast-math (ARM)
On 29 March 2017 at 02:33, Saleem Abdulrasool <compnerd at compnerd.org> wrote: > sin/cos are libm functions, and so a libcall to those need to honour the > floating point ABI requests. The calling convention to be followed there > should match `-mfloat-abi` (that is, -mfloat-abi=hard => AAPCS/VFP, > -mfloat-abi=soft => AAPCS). Exactly, but they're not, and that's
2015 Jan 30
1
[LLVMdev] Different instruction encodings based on subtarget features
I am working on an LLVM backend for the AVR architecture, and am having troubles working with the codegen layer, trying to get around the quirks of the binary encodings of the AVR ISR. There are several different families of AVR microcontrollers, each with a minimum 'core' instruction set. Each family builds upon (or removes) the core ISR with more instructions or different encodings. My
2017 Jun 21
2
Verifying Backend Schedule (Over)Coverage
I ran into an interesting problem when helping to land a scheduler .td file that my colleague had written. The problem that came up was that a multiply/add pair was not combined into an madd, but just for our CPU. Upon digging into it, the problem turned out to be that '(instregex "^SUB" ...' was matching "SUBREG_TO_REG" and incorrectly increasing the schedule length.
2019 Apr 01
3
Please expose predicates to MachineVerifier
Could we expose predicates defined in the target InstrInfo.td file to the MachineVerifier? We use BuildMI() to create many instructions after ISEL, but the predicates are not being checked at this point. Thus, I could forget to check the target and build an instruction that is illegal for a specific configuration. In such a case it would be nice if the MachineVerifier could detect this for me.
2012 Oct 15
2
[LLVMdev] Alternate instruction encoding for subtargets
Hello, I have a compiler in LLVM 2.9 for the KCPM3 processor. I'd like to create a subtarget for the new cpu version called KCPSM6. Besides a couple of new instructions which are not important at the moment, the KCPSM6 cpu has different instruction opcodes. Semantically the instructions are the same, hence I'd like to keep all the lowering and pattern matching stuff unmodified For
2010 Apr 04
1
[LLVMdev] How to specify the subtarget instruction set for LLVM unit in ARM-backend?
Dear developers! I’d like to ask you a question concerning the implementation of one algorithm for the generation of energy-efficient code for ARM processors. Unfortunately, the documentation on this subject is incomplete on your site, so could you please explain how to implement my algorithm. Without going into details, I would like to say, that the implementation of this algorithm
2010 Oct 24
1
[LLVMdev] How to specify the arm subtarget instruction set in a pass or an arm-backend?
Dear developers! I have one problem and two options for its solution: • I can make a simple pass which will specify the subtarget instruction set (ARM or Thumb) for a particular instruction (or a basic block) LLVM intermediate representation OR • I can add a special pass to arm backend which will do the same (specify subtarget instruction set (ARM or Thumb) for a particular