search for: subtarget

Hi all, I have a sample test case : $ cat 1.c int foo(int x, int y){ int z = x + y; return z/2; } I tried to get its IR form with clang providing subtarget feature as mmx for target x86_64 $ clang -O3 -mmmx 1.c -S -emit-llvm in the IR generated i can see the subtarget-features as function attribute : "target-features"="+mmx" In the SelectionDAG phase in file "X86ISelLowering.cpp", i checked in one of the function wha...

Hi, I found some different discrepancy on how Subtarget is created between some arch specific TargetMachine constructor. For example, for BPF/Lanai: BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Opt...

Hi, while implementing SystemZTTI:getCacheSize(), it became clear that there really isn't a simple way to just ask the Subtarget for the current subtarget machine model. I was thinking like something of an enum that would also reflect the subtarget series (and would allow >= and similar operations). I would like to ask what the ideas are on how this should be done best. Some thoughts: * Just comparing the CPU string...

[resending to correct llvm-dev address] Hi, I’d like to start enabling the loop data prefetch pass for Cyclone (an ARM64 subtarget). AFAICT, you can’t really add passes specifically to a subtarget but only to a target. This makes sense because in the new world, you could have different subtargets per function. I just want to make sure my understanding is correct. My plan is to add the pass for the target and then exit the...

I've been trying to understand the current state of subtargets and subtarget features in LLVM. It seems like the presence of "target-cpu" and "target-features" attributes on IR functions are currently intended to take precedence over the module-level (TargetMachine) versions. See X86TargetMachine::getSubtargetImpl for an example of thi...

Hello llvm-dev, Following up on the "CodeGen Context" discussion that was started, attached is patch which implements a pretty minimal skeleton of a CGContext implementation. The goal is to allow the newly added subtarget attributes on functions to be made available to codegen so that codegen can actually switch subtargets within a Module. Comments and questions are invited herewith. There has been some disagreement as to what to name this class. I have stuck with "CGContext" for now, though I'm abso...

...an433584 at gmail.com> wrote: > > > Hello llvm-dev, > > > > Following up on the "CodeGen Context" discussion that was started, > attached is patch which implements a pretty minimal skeleton of a CGContext > implementation. The goal is to allow the newly added subtarget attributes > on functions to be made available to codegen so that codegen can actually > switch subtargets within a Module. > > > > Comments and questions are invited herewith. > > > > There has been some disagreement as to what to name this class. I have > stuck wi...

...lers.llvm.devel/80456 The command line options I'm currently looking into are "-target-cpu" and "-target-feature" and I would like to get feedback about the approach I've taken (patches attached). The attached patches make the following changes: - In TargetMachine::getSubtarget(const Function*) and MachineFunction's constructor, use per-function subtarget object instead of TargetMachine's (module-level) subtarget object. This allows passes like selection dag to switch the target on a per-function basis. - Define class TargetOptions::Option, which records whether...

...ex. See my comments below. On Wed, Aug 23, 2017 at 12:59 AM, Alex Bradbury <asb at asbradbury.org> wrote: > On 22 August 2017 at 23:39, Y Song via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> Hi, > > Hi Yonghong. > >> I found some different discrepancy on how Subtarget is created >> between some arch specific TargetMachine constructor. >> For example, for BPF/Lanai: >> >> <snip> >> >> Note that Subtarget is created as part of constructor. On the other hard, >> initAsmInfo() tries to create a subtargetinfo as well. T...

...at 4:40 PM, Dan Gohman <dan433584 at gmail.com> wrote: > Hello llvm-dev, > > Following up on the "CodeGen Context" discussion that was started, attached is patch which implements a pretty minimal skeleton of a CGContext implementation. The goal is to allow the newly added subtarget attributes on functions to be made available to codegen so that codegen can actually switch subtargets within a Module. > > Comments and questions are invited herewith. > > There has been some disagreement as to what to name this class. I have stuck with "CGContext" for now,...

...; > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09, 2015 11:27 AM > *To:* LLVM Developers Mailing List; David Majnemer; Sanjay Patel > *Subject:* [LLVMdev] MMX/SSE subtarget feature in IR > > > > Hi all, > > > > I have a sample test case : > > > > $ cat 1.c > > > > int foo(int x, int y){ > > int z = x + y; > > return z/2; > > } > > > > I tried to get its IR form with clang providing subta...

...llowering.cpp static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT, SDValue V1, SDValue V2, const SmallBitVector &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG) { // If we have a single input to the zero element, insert that into V1 if we // can do so cheaply. int NumElts = Mask.size(); int NumV2Elements = count_if(Mask, [NumElts](int M) { return M >= NumElts; });...

...for a given memory region by an attribute in a memory area descriptor. Targets supporting this that I know of are all bare-metal (so powerpc-none-elf). I'm trying to implement ELF support right now. VLE ELF files should have a section header flag set (SHF_PPC_VLE = 0x10000000). I have added a subtarget feature "vle", similar to Altivec, SPE, VSX etc and I'm enabling this feature for appropriate CPUs. Now, functions that are compiled with "vle" feature should go into a different text section (text_vle). I can see that TargetMachine has a method getSubtargetImpl which can b...

On 29 March 2017 at 02:33, Saleem Abdulrasool <compnerd at compnerd.org> wrote: > sin/cos are libm functions, and so a libcall to those need to honour the > floating point ABI requests. The calling convention to be followed there > should match `-mfloat-abi` (that is, -mfloat-abi=hard => AAPCS/VFP, > -mfloat-abi=soft => AAPCS). Exactly, but they're not, and that's

...odings. My context is that the binary encodings of certain instructions differ solely with the 'AVR Tiny' family of devices (see the bottom row of the tabled headed "Instruction set inheritance" linked here <http://en.wikipedia.org/wiki/Atmel_AVR_instruction_set>). I have a subtarget feature specifically for each CPU family. What I would like to do is choose a different instruction encoding based on whether or not the 'AVR Tiny' subtarget feature is enabled. I have found this <http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-November/055149.html> link to a LLVMdev...

...ched multiple regex patterns in InstegexOp::apply in utils/TableGen/CodeGenSchedule. I modified the apply method to output <idx, pat> pairs and <idx, name> pairs and then joined them togather using a script. However, I couldn't easily determine from within that method what specific subtarget the patterns came from. Is there a better place to do this check? It seems that CodeGenSchedModels::checkCompleteness would be the logical place. Joel Jones

...is for me. Example predicate IsCore8 usage: def ADDx: BINOP<...>, Requires<[IsCore8]>; let Predicates=[IsCore8] in { def : SUBX: BINOP<...>; } The predicates are encoded into the targets GenDAGIsel file but not anywhere else that I can find: OPC_CheckPatternPredicate, 4, // (Subtarget.isCore8()) Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190401/b46c6b83/attachment.html>

Hello, I have a compiler in LLVM 2.9 for the KCPM3 processor. I'd like to create a subtarget for the new cpu version called KCPSM6. Besides a couple of new instructions which are not important at the moment, the KCPSM6 cpu has different instruction opcodes. Semantically the instructions are the same, hence I'd like to keep all the lowering and pattern matching stuff unmodified For exa...

...icient code for ARM processors. Unfortunately, the documentation on this subject is incomplete on your site, so could you please explain how to implement my algorithm. Without going into details, I would like to say, that the implementation of this algorithm requires the ability to specify the subtarget instruction set (ARM or Thumb) for a particular instruction LLVM intermediate representation. If at this stage of development, your compiler does not support this feature, please specify the minimal unit (basic block, entire function or anything else) that the current version of the compiler i...

Dear developers! I have one problem and two options for its solution: • I can make a simple pass which will specify the subtarget instruction set (ARM or Thumb) for a particular instruction (or a basic block) LLVM intermediate representation OR • I can add a special pass to arm backend which will do the same (specify subtarget instruction set (ARM or Thumb) for a particular instruction or basic block LLVM intermediate r...