Displaying 20 results from an estimated 28 matches for "subregclasses".
Did you mean:
subregclass
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...elow functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
/// getSuperRegisterRegClass - Returns the register class of a superreg
A whose
/// "SubIdx"'th sub-register class is the spe...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...t;
>>> static const TargetRegisterClass*
>>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
>>> SubIdx)
>>> {
>>> // Pick the register class of the subregister
>>> TargetRegisterInfo::regclass_iterator I =
>>> TRC->subregclasses_begin() + SubIdx-1;
>>> assert(I < TRC->subregclasses_end() &&
>>> "Invalid subregister index for register class");
>>> return *I;
>>> }
>>>
>>> what does -1 do while initializing I in the above fn?
>>>
&g...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...argetRegisterClass*
> >>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
> >>> SubIdx)
> >>> {
> >>> // Pick the register class of the subregister
> >>> TargetRegisterInfo::regclass_iterator I =
> >>> TRC->subregclasses_begin() + SubIdx-1;
> >>> assert(I < TRC->subregclasses_end() &&
> >>> "Invalid subregister index for register class");
> >>> return *I;
> >>> }
> >>>
> >>> what does -1 do while initializing I in...
2008 Oct 20
1
[LLVMdev] INSERT_SUBREG node.
On Mon, 2008-10-20 at 08:07 -0700, Evan Cheng wrote:
> On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:
>
> >>>
> >>> PR2916 filed.
> >>> Though I did not quite understand why this could be a tablegen bug?
> >>
> >>
> >> Based on your comments. :-) It should be possible to specify two FSR0
> >> sub-registers (FSR0L,
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...t_subreg implicit_def, v1, 0
the following function returns an incorrect subregclass:
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
what does -1 do while initializing I in the above fn?
TIA,
Sanjiv
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...owing function returns an incorrect subregclass:
>
> static const TargetRegisterClass*
> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
> SubIdx)
> {
> // Pick the register class of the subregister
> TargetRegisterInfo::regclass_iterator I =
> TRC->subregclasses_begin() + SubIdx-1;
> assert(I < TRC->subregclasses_end() &&
> "Invalid subregister index for register class");
> return *I;
> }
>
> what does -1 do while initializing I in the above fn?
>
> TIA,
> Sanjiv
>
>
>
> _____________...
2008 Oct 20
2
[LLVMdev] INSERT_SUBREG node.
On Sun, 2008-10-19 at 23:18 -0700, Evan Cheng wrote:
>
> On Oct 18, 2008, at 7:01 AM, sanjiv gupta wrote:
>
> > On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote:
> > > On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote:
> > >
> > > > > >
> > > > >
> > > > > Ok. The AX / AH super-reg and sub-reg relationship is
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote:
> On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote:
>
> >>>
> >>
> >> Ok. The AX / AH super-reg and sub-reg relationship is not defined. In
> >> general x86 is not making good use of the high 8-bit sub-registers.
> >> We
> >> are leaving some performance on the table. We'll
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...s*
>>>>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
>>>>> SubIdx)
>>>>> {
>>>>> // Pick the register class of the subregister
>>>>> TargetRegisterInfo::regclass_iterator I =
>>>>> TRC->subregclasses_begin() + SubIdx-1;
>>>>> assert(I < TRC->subregclasses_end() &&
>>>>> "Invalid subregister index for register class");
>>>>> return *I;
>>>>> }
>>>>>
>>>>> what does -1 do while...
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D2, D3, D4, D5, D6, D7,
> D8, D9, D10, D11, D12, D13, D14, D15)>;
>
> // Extended-size data register class
> def ER : RegisterClass<"TriCore", [i64], 32,
> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
> let SubRegClasses = [(DR sub_even, sub_odd)];
> }
>
> And the DX and EX registers are defined this way:
The regclasses look fine... So, you need to figure out why
getRepRegClassFor() returns NULL in this case.
Side note: you can autogenerate register names :)
--
With best regards, Anton Korobeynikov
Facul...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:
>>>
>>> PR2916 filed.
>>> Though I did not quite understand why this could be a tablegen bug?
>>
>>
>> Based on your comments. :-) It should be possible to specify two FSR0
>> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
>> workaround you described:
>>
>>
2011 Aug 25
2
[LLVMdev] AVX spill alignment
Hey guys,
Are spills/reloads of AVX registers using aligned stores/loads? I can't
seem to find the code that aligns the stack slots to 32-bytes. Could
someone point me in the right direction?
Thanks,
Cameron
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110825/b5724dec/attachment.html>
2011 Sep 01
0
[LLVMdev] AVX spill alignment
...he stack slots to 32-bytes. Could
> someone point me in the right direction?
The register class has 256-bit spill alignment:
def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
256, (sequence "YMM%u", 0, 15)> {
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
}
/jakob
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
> This isn't really my area of expertise, but I think you're messing up
> your RegisterClass definition. Look at how ARM defines DTriple.
DTriple is untyped :) , because we do not have any valut type which
defines 3xi64.
However, the paired register needs to have type.
Fabian, what are the definitions of ER and DR register classes?
--
With best regards, Anton Korobeynikov
Faculty
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...(add D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15)>;
// Extended-size data register class
def ER : RegisterClass<"TriCore", [i64], 32,
(add E0, E2, E4, E6, E8, E10, E12, E14)> {
let SubRegClasses = [(DR sub_even, sub_odd)];
}
And the DX and EX registers are defined this way:
def D0 : TriCoreReg<0, "d0">, DwarfRegNum<[0]>;
...
def D15 : TriCoreReg<15, "d15">, DwarfRegNum<[15]>;
def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]...
2012 Aug 22
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D8, D9, D10, D11, D12, D13, D14, D15)>;
>>>
>>> // Extended-size data register class
>>> def ER : RegisterClass<"TriCore", [i64], 32,
>>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>>> let SubRegClasses = [(DR sub_even, sub_odd)];
>>> }
>>>
>>> And the DX and EX registers are defined this way:
>> The regclasses look fine... So, you need to figure out why
>> getRepRegClassFor() returns NULL in this case.
> Well, that's rather easy :-) The register class...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
On Oct 18, 2008, at 7:01 AM, sanjiv gupta wrote:
> On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote:
>> On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote:
>>
>>>>>
>>>>
>>>> Ok. The AX / AH super-reg and sub-reg relationship is not
>>>> defined. In
>>>> general x86 is not making good use of the high 8-bit
2012 Aug 22
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D7,
>> D8, D9, D10, D11, D12, D13, D14, D15)>;
>>
>> // Extended-size data register class
>> def ER : RegisterClass<"TriCore", [i64], 32,
>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>> let SubRegClasses = [(DR sub_even, sub_odd)];
>> }
>>
>> And the DX and EX registers are defined this way:
> The regclasses look fine... So, you need to figure out why
> getRepRegClassFor() returns NULL in this case.
Well, that's rather easy :-) The register class is not registered in
th...
2011 May 09
2
[LLVMdev] wide memory accesses
...e able to use 32 bit registers with a subregister index. Is this possible, or need I make a new register class where all these are included in a blended fashion: 16/32 bits, and use this instead for the instruction?
I have defined the 16 bit registers as subregs to the 32 bits. I have also defined subregclasses, as per let SubRegClasses =...
2. Insert COPY's, but these would not get coalesced away, so instead of saving instructions I ended up with one load and two moves...:-( How could I get the wide load to simply be used intelligently by COPYing to the old virtual registers?
I would appreciate a...
2011 Sep 01
1
[LLVMdev] AVX spill alignment
...uld
>> someone point me in the right direction?
>
> The register class has 256-bit spill alignment:
>
> def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32,
v4f64],
> 256, (sequence "YMM%u", 0, 15)> {
> let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
> }
>
> /jakob
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110901/3403477c/attachment.html>