Displaying 20 results from an estimated 28 matches for "subregclass".
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...;(i32 0)>;
def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
class GR16_ ..... {
let SubRegClassList = [GR8];
}
Refer to below functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regcla...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...Set<0, [AX, CX, DX, BX, SP, BP, SI, DI,
> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
>
>
> class GR16_ ..... {
> let SubRegClassList = [GR8];
> }
Right. Subreg index starts from 1. This ought to be fixed but it's not
(yet).
>
>
> The getSubRegisterRegClass uses SubIdx - 1;
>
> so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> getSubRegisterRegClass will fail.(GR16_ does not ha...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...SI, DI,
> > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> > [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> > R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
> >
> >
> > class GR16_ ..... {
> > let SubRegClassList = [GR8];
> > }
>
> Right. Subreg index starts from 1. This ought to be fixed but it's not
> (yet).
>
> >
> >
> > The getSubRegisterRegClass uses SubIdx - 1;
> >
> > so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> &...
2008 Oct 20
1
[LLVMdev] INSERT_SUBREG node.
...should be possible to specify two FSR0
> >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
> >> workaround you described:
> >>
> >>
> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> >> let SubRegClassList = [FSR8, FSR8]; // HERE.
> >> }
> >>
> > It is currently possible.
>
> I am confused. Is what you described in PR2916 an issue or not?
>
is specifying the same subregclass two times okay? or do we need to
cleanup the implementation so that you specify a SubR...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...;"FSR0", [FSR0H, FSR0L]>;
def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L,
FSR1H]>;
def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {
let SubRegClassList = [FSR8RC];
}
in my case I want to insert two values, which are available in register
types of FSR8RC, into a register type of FSR16RC.
when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in
> v4= insert_subreg implicit_def, v1, 0
the following function returns an incorr...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...R0L]>;
> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
>
> def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L,
> FSR1H]>;
>
> def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {
> let SubRegClassList = [FSR8RC];
> }
>
> in my case I want to insert two values, which are available in
> register
> types of FSR8RC, into a register type of FSR16RC.
>
> when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in
>
>> v4= insert_subreg implicit_def, v1, 0...
2008 Oct 20
2
[LLVMdev] INSERT_SUBREG node.
...gt; > it is, though we have a workaround.
> > > >
> > > > We have 16-bit registers class and want to set both the lo and
> > > > high
> > > > parts using INSERT_SUBREG.
> > > >
> > > > The workaround is to declare the same SubRegClass twice while
> > > > declaring
> > > > the SuperRegisterClass. i.e.
> > > >
> > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > > > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > > > }...
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
...e of insert_subreg, no?
> >>
> >> Evan
> >>
> > it is, though we have a workaround.
> >
> > We have 16-bit registers class and want to set both the lo and high
> > parts using INSERT_SUBREG.
> >
> > The workaround is to declare the same SubRegClass twice while
> > declaring
> > the SuperRegisterClass. i.e.
> >
> > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > }
>
> This is a bug, probably in tablegen. Unfortunate...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...ying the sub-registers and making
>> use of insert_subreg, no?
>>
>> Evan
>>
> it is, though we have a workaround.
>
> We have 16-bit registers class and want to set both the lo and high
> parts using INSERT_SUBREG.
>
> The workaround is to declare the same SubRegClass twice while
> declaring
> the SuperRegisterClass. i.e.
>
> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> let SubRegClassList = [FSR8, FSR8]; // HERE.
> }
This is a bug, probably in tablegen. Unfortunately I don't have the
time to fix it...
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D2, D3, D4, D5, D6, D7,
> D8, D9, D10, D11, D12, D13, D14, D15)>;
>
> // Extended-size data register class
> def ER : RegisterClass<"TriCore", [i64], 32,
> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
> let SubRegClasses = [(DR sub_even, sub_odd)];
> }
>
> And the DX and EX registers are defined this way:
The regclasses look fine... So, you need to figure out why
getRepRegClassFor() returns NULL in this case.
Side note: you can autogenerate register names :)
--
With best regards, Anton Korobeynikov
Fac...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...ased on your comments. :-) It should be possible to specify two FSR0
>> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
>> workaround you described:
>>
>>
>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>> }
>>
> It is currently possible.
I am confused. Is what you described in PR2916 an issue or not?
Evan
>
>
> - Sanjiv
>
>>
>> Evan
>>
>>>
>>>
>>> - Sanjiv
>>>
>>>
>>&g...
2011 Aug 25
2
[LLVMdev] AVX spill alignment
Hey guys,
Are spills/reloads of AVX registers using aligned stores/loads? I can't
seem to find the code that aligns the stack slots to 32-bytes. Could
someone point me in the right direction?
Thanks,
Cameron
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2011 Sep 01
0
[LLVMdev] AVX spill alignment
...he stack slots to 32-bytes. Could
> someone point me in the right direction?
The register class has 256-bit spill alignment:
def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
256, (sequence "YMM%u", 0, 15)> {
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
}
/jakob
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
> This isn't really my area of expertise, but I think you're messing up
> your RegisterClass definition. Look at how ARM defines DTriple.
DTriple is untyped :) , because we do not have any valut type which
defines 3xi64.
However, the paired register needs to have type.
Fabian, what are the definitions of ER and DR register classes?
--
With best regards, Anton Korobeynikov
Faculty
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...(add D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15)>;
// Extended-size data register class
def ER : RegisterClass<"TriCore", [i64], 32,
(add E0, E2, E4, E6, E8, E10, E12, E14)> {
let SubRegClasses = [(DR sub_even, sub_odd)];
}
And the DX and EX registers are defined this way:
def D0 : TriCoreReg<0, "d0">, DwarfRegNum<[0]>;
...
def D15 : TriCoreReg<15, "d15">, DwarfRegNum<[15]>;
def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D...
2012 Aug 22
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D8, D9, D10, D11, D12, D13, D14, D15)>;
>>>
>>> // Extended-size data register class
>>> def ER : RegisterClass<"TriCore", [i64], 32,
>>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>>> let SubRegClasses = [(DR sub_even, sub_odd)];
>>> }
>>>
>>> And the DX and EX registers are defined this way:
>> The regclasses look fine... So, you need to figure out why
>> getRepRegClassFor() returns NULL in this case.
> Well, that's rather easy :-) The register cla...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...;>>>
>>>> Evan
>>>>
>>> it is, though we have a workaround.
>>>
>>> We have 16-bit registers class and want to set both the lo and high
>>> parts using INSERT_SUBREG.
>>>
>>> The workaround is to declare the same SubRegClass twice while
>>> declaring
>>> the SuperRegisterClass. i.e.
>>>
>>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>>> }
>>
>> This is a bug, probably in...
2012 Aug 22
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D7,
>> D8, D9, D10, D11, D12, D13, D14, D15)>;
>>
>> // Extended-size data register class
>> def ER : RegisterClass<"TriCore", [i64], 32,
>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>> let SubRegClasses = [(DR sub_even, sub_odd)];
>> }
>>
>> And the DX and EX registers are defined this way:
> The regclasses look fine... So, you need to figure out why
> getRepRegClassFor() returns NULL in this case.
Well, that's rather easy :-) The register class is not registered in...
2011 May 09
2
[LLVMdev] wide memory accesses
...e able to use 32 bit registers with a subregister index. Is this possible, or need I make a new register class where all these are included in a blended fashion: 16/32 bits, and use this instead for the instruction?
I have defined the 16 bit registers as subregs to the 32 bits. I have also defined subregclasses, as per let SubRegClasses =...
2. Insert COPY's, but these would not get coalesced away, so instead of saving instructions I ended up with one load and two moves...:-( How could I get the wide load to simply be used intelligently by COPYing to the old virtual registers?
I would appreciate...
2011 Sep 01
1
[LLVMdev] AVX spill alignment
...uld
>> someone point me in the right direction?
>
> The register class has 256-bit spill alignment:
>
> def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32,
v4f64],
> 256, (sequence "YMM%u", 0, 15)> {
> let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
> }
>
> /jakob
>
>
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