search for: subidx

...[AL, CL, DL, BL, SPL, BPL, SIL, DIL, > R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; > > I admit the way it's specified is not very elegant. We'll clean it up > some day. > > Evan > Even in that case you can not have a 0 as a SubIdx. e.g. the code below won't work def x86_subreg_8bit : PatLeaf<(i32 0)>; def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], [AL, CL, DL, BL, SPL, BPL, SIL, DIL, R8B,...

...0L, FSR1H]>; def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> { let SubRegClassList = [FSR8RC]; } in my case I want to insert two values, which are available in register types of FSR8RC, into a register type of FSR16RC. when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in > v4= insert_subreg implicit_def, v1, 0 the following function returns an incorrect subregclass: static const TargetRegisterClass* getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) { // Pick the register class of the subregister TargetRegist...

...sterClass<"PIC16", [i16], 8, [FSR0, FSR1]> { > let SubRegClassList = [FSR8RC]; > } > > in my case I want to insert two values, which are available in > register > types of FSR8RC, into a register type of FSR16RC. > > when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in > >> v4= insert_subreg implicit_def, v1, 0 > > the following function returns an incorrect subregclass: > > static const TargetRegisterClass* > getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned > SubIdx) > { > // Pick the re...

...BL, SPL, BPL, SIL, DIL, >> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; >> >> I admit the way it's specified is not very elegant. We'll clean it up >> some day. >> >> Evan >> > Even in that case you can not have a 0 as a SubIdx. > e.g. the code below won't work > > def x86_subreg_8bit : PatLeaf<(i32 0)>; > > > def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI, > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], > [AL, CL, DL, BL, SPL, BPL, SI...

...VM about the 6502's registers, but, for now, I want to see how far I can get using the allocator as intended. The registers are A, X, and Y. They belong to a hierarchy of Register Classes: Acc class: A Index class: X, Y General class: Acc, Index There's a fictional instruction "SUBidx Acc, Index". It subtracts an Index from an Acc. Bear with me. What if we want to subtract A from X? We can't say "SUBidx X, A". The operands must be Acc, Index. The DAG looks something like this: %vreg2 = COPY %X ; %vreg2 is Index %vreg0 = COPY %A ; %vreg0 is Acc SUBidx...

...R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; > >> > >> I admit the way it's specified is not very elegant. We'll clean it up > >> some day. > >> > >> Evan > >> > > Even in that case you can not have a 0 as a SubIdx. > > e.g. the code below won't work > > > > def x86_subreg_8bit : PatLeaf<(i32 0)>; > > > > > > def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI, > > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], > >...

...ut please file a bug about this. Hopefully someone will fix it soon. Thanks, Evan > > > SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>; > SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>; > > > I think the fundamental problem we have there is that we are using > SubIdx for both purposes: 1. to enumerate over subregister > classses, 2. > To enumerate subregs of the same type of a super reg. > > > - Sanjiv. > >>> >>> >>> >>> Hope I made it clear. Please write back if they aren't. >>> >>>...

On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > What’s the value produced by an INSERT_SUBREG node? Is it a chain? No, insert_subreg returns a value: v1 = insert_subreg v2, v3, idx v1 and v2 will have the same type, e.g. i16, and v3 must have a sub- register type, e.g. i8. > Can I use to set a superreg of i16 type with two i8 values, and use > the supperreg as

What's the value produced by an INSERT_SUBREG node? Is it a chain? Can I use to set a superreg of i16 type with two i8 values, and use the supperreg as an operand somewhere else? - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081002/f07bc88c/attachment.html>

...it may be good to push/pop R8 for R8D (i.e I don't want to change current implementation which inserts MI for CSR) for that I need to find biggest register for which given register is alias like R8 has R8D as alias. How can I find that? I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) but here I don't know what will be SubIdx for given Reg in given RC. So for example if a function which should be optimized for above optimization is having following set of clobbered registers: R8D,R8, ECX, EAX, RAX, ESI It should push/pop R8, RCX, RAX, RSI. P...

...dMemoryOperand() if it matters). Obviously I need > to make some changes. But what? This is quite simple to handle. A register MachineOperand has a subreg field for this purpose. It is used to pick out subregisters of a virtual register. For a physical register: MO.setReg(TRI.getSubReg(Reg, SubIdx)); For a virtual register: MO.setReg(Reg); MO.setSubReg(SubIdx); If you are using BuildMI, the subreg is passed as the third argument to addReg(). The register allocator (rewriter to be exact) will clear the subreg field when substituting the allocated physical register. Note that a physic...

...> It is currently possible. > > I am confused. Is what you described in PR2916 an issue or not? > is specifying the same subregclass two times okay? or do we need to cleanup the implementation so that you specify a SubRegClass only once. The other related issue is that we can not use SubIdx starting from Zero. - Sanjiv > Evan > > > > > > > - Sanjiv > > > >> > >> Evan > >> > >>> > >>> > >>> - Sanjiv > >>> > >>> > >>> _______________________________________...

...ush/pop R8 for R8D (i.e I > don't want to change current implementation which inserts MI for > CSR) for that I need to find biggest register for which given > register is alias like R8 has R8D as alias. How can I find that? > I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx, > const TargetRegisterClass *RC) but here I don't know what will be > SubIdx for given Reg in given RC. > > > So for example if a function which should be optimized for above > optimization is having following set of clobbered registers: > R8D,R8, ECX, EAX, RAX, ESI It s...

On Sat, Jul 9, 2016 at 12:18 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Jul 8, 2016, at 11:41 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > On Fri, Jul 8, 2016 at 11:46 PM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On Jul 8, 2016, at 11:12 AM, vivek pandya <vivekvpandya at gmail.com> wrote:

Does anybody have any tips for generating spills/reloads for large non-vector registers? I'm working on a back end for a DSP architecture that has accumulator registers that are too large to be spilled or reloaded with a single instruction. All of their bits can be accessed in word-size chunks via three sub-registers (low, high, and ext). So loading or storing one requires three instructions:

...y be good to push/pop R8 for R8D (i.e I don't want to change current implementation which inserts MI for CSR) for that I need to find biggest register for which given register is alias like R8 has R8D as alias. How can I find that? > I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) but here I don't know what will be SubIdx for given Reg in given RC. If you create a function with a “preserve_all” CC and put some inline assembly that clobbers r8d, I expect we’re already generating the correct push (outside of IPRA), right? I’d start by figur...

...i.e I > > don't want to change current implementation which inserts MI for > > CSR) for that I need to find biggest register for which given > > register is alias like R8 has R8D as alias. How can I find that? > > I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx, > > const TargetRegisterClass *RC) but here I don't know what will be > > SubIdx for given Reg in given RC. > > > > > > So for example if a function which should be optimized for above > > optimization is having following set of clobbered registers: > &gt...

...change current implementation which inserts MI for > > > > CSR) for that I need to find biggest register for which given > > > > register is alias like R8 has R8D as alias. How can I find that? > > > > I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx, > > > > const TargetRegisterClass *RC) but here I don't know what will be > > > > SubIdx for given Reg in given RC. > > > > > > > > > > > > So for example if a function which should be optimized for above > > > > opt...

Hello, I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register. Example of an addition: load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1 load b, reg1; // -> copies old value of reg1 in reg2 and loads

...i.e I > > don't want to change current implementation which inserts MI for > > CSR) for that I need to find biggest register for which given > > register is alias like R8 has R8D as alias. How can I find that? > > I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx, > > const TargetRegisterClass *RC) but here I don't know what will be > > SubIdx for given Reg in given RC. > > > > > > So for example if a function which should be optimized for above > > optimization is having following set of clobbered registers: > &gt...