search for: subcc

There is format in sparc <pre> subcc %r1, %r2, %r3 bne .label </pre> I want instruction like this <pre> bne %r1, %r2, .label </pre> </BR> I am referring to sparc code for this implementation (llvm-3.1).</BR></BR> 1. Should I change the SPBranch and BCOND structs in .td file.</BR> 2. Should I...

...1, [%fp+-12] sethi %hi(.L.str), %l1 ld [%fp+-8], %o1 add %l1, %lo(.L.str), %l1 or %g0, %l1, %o0 call printf nop ld [%fp+-12], %o2 ld [%fp+-8], %l2 sethi %hi(.L.strQ521), %l3 add %l3, %lo(.L.strQ521), %o0 or %g0, %l2, %o1 call MY_FUNCTION nop or %g0, 1, %i0 (subcc %l1, 0, %l1 ! This line is added by me. It was not there) bne .LBB0_2 nop ! BB#1: subcc %l2, 0, %l2 or %g0, %l0, %i0 .LBB0_2: ....... I am not an expert on Sparc assembly, but I read from somewhere that branching instructions are set by the statues flags. The first '...

Hi Christine, > I am using LLVM 2.8 and llvm-gcc 4.2. Could you please try svn top-of-tree? Clang is also a better choice here. > The assembly files are attached. In the assembly file, the erroneous result > is associated with 'subcc', while the correct ones are associated with 'or'. -- Bruno Cardoso Lopes http://www.brunocardoso.cc

...gmail.com> wrote: > Hi Christine, > >> I am using LLVM 2.8 and llvm-gcc 4.2. > > Could you please try svn top-of-tree? Clang is also a better choice here. > >> The assembly files are attached. In the assembly file, the erroneous result >> is associated with 'subcc', while the correct ones are associated with 'or'. > > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc >

...F3_12<"add" , 0b000000, add>; defm ADDCC : F3_12<"addcc", 0b010000, addc>; defm ADDX : F3_12<"addx" , 0b001000, adde>; defm SUB : F3_12<"sub" , 0b000100, sub>; defm SUBX : F3_12<"subx" , 0b001100, sube>; defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>; ... Each of these 'defm's expand into two instructions. > The semantic of such a description would mean that $dst should be one > of GR8, GR16, GR32 and $dst is one of i8mem, i16mem, i32mem with the > additional constraint th...

Hi Venkatraman, I am using LLVM 2.8 and llvm-gcc 4.2. The assembly files are attached. In the assembly file, the erroneous result is associated with 'subcc', while the correct ones are associated with 'or'. Thanks a lot! Christine On Fri, Sep 16, 2011 at 2:29 PM, Venkatraman Govindaraju < venkatra at cs.wisc.edu> wrote: > Hello, > > What is your LLVM version? Also, can you attach the assembly generated? > > Thanks...

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty

Hello, What is your LLVM version? Also, can you attach the assembly generated? Thanks, Venkatraman On Thu, Sep 15, 2011 at 5:20 PM, Bruno Cardoso Lopes <bruno.cardoso at gmail.com> wrote: > Hi, > > On Thu, Sep 15, 2011 at 3:15 PM, Christine Cheng <clcheng at stanford.edu> wrote: >> Hi guys, >> >> Thanks for the input. However, it seems that the code

Hi, Have you try to directly describe such patterns in tblgen file? Like this: (brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset) MIPS backend does that. I also do this in my own backend, and seem to be working fine. On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com> wrote: > I have seen that most of the targets do comparison and branching > in two separate

...sethi 4194296, %g1 or %g1, 56, %g1 save %g1, %o6, %o6 sethi 0, %l0 The nop right before sethi is one instruction I'm not being able to reach in my pass. But there is more: add %l0, 1, %l0 st %l0, [%i6+-12] .BB1_2: ! bb8 ld [%i6+-12], %l0 subcc %l0, 1000, %l0 bl .BB1_1 ! bb nop .BB1_3: ! bb12 ba .BB1_5 ! bb19 nop or %g0, 1, %l0 Here both the "ba" and the "nop", that are the 3rd and 2nd last operations of this snipet, are not reachable. Could I express myself good en...

I have seen that most of the targets do comparison and branching in two separate instructions e.g. 'cmpl' followed by 'br' in x86 or the like. LLVM IR is also in same manner. I want to implement comparison+branching in one instruction like beq r1, r2, .label #if r1==r2 then jump to .label How to merge two instruction into one. Regards Vikram Singh -- View this

...ors according to CFG: BB#314 %reg1731<def> = SETHIi 1856 %reg1732<def> = ORri %G0, 1 %reg1733<def> = SLLrr %reg1732, %reg1729 %reg1734<def> = ORri %reg1731, 1 %reg1735<def> = ANDrr %reg1733, %reg1734 %reg1736<def> = SUBCCri %reg1735, 0, %ICC<imp-def> BCOND <BB#3>, 9, %ICC<imp-use> BA <BB#53> Successors according to CFG: BB#3 BB#53 BB#3: derived from LLVM BB %bb1 Predecessors according to CFG: BB#315 %reg1740<def> = ANDri %reg1067, 255 %reg1741&lt...

..., 0b000000, add>; > defm ADDCC : F3_12<"addcc", 0b010000, addc>; > defm ADDX : F3_12<"addx" , 0b001000, adde>; > defm SUB : F3_12<"sub" , 0b000100, sub>; > defm SUBX : F3_12<"subx" , 0b001100, sube>; > defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>; > ... > > Each of these 'defm's expand into two instructions. > >> The semantic of such a description would mean that $dst should be one >> of GR8, GR16, GR32 and $dst is one of i8mem, i16mem, i32mem with the &...

...R, Q, and V are inputs and outputs as defined above; + * the condition codes are expected to reflect the input R, and are + * modified to reflect the output R. + */ +define(DEVELOP_QUOTIENT_BITS, +` ! depth $1, accumulated bits $2 + bl L.$1.eval(TWOSUPN+$2) + srl V,1,V + ! remainder is positive + subcc R,V,R + ifelse($1, N, + ` b 9f + add Q, ($2*2+1), Q + ', ` DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2+1)')') +L.$1.eval(TWOSUPN+$2): + ! remainder is negative + addcc R,V,R + ifelse($1, N, + ` b 9f + add Q, ($2*2-1), Q + ', ` DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2-1)')'...

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

I have updated the klibc patchset based on feedback received. In particular, the patchset has been reorganized so as not to break git-bisect. Additionally, this updates the patch base to 2.6.17-git12 (d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main difference on the klibc side is removal of obsolete code. This is also available as a git tree at: