Displaying 12 results from an estimated 12 matches for "sub_odd".
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sub_id
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...t; D8, D9, D10, D11, D12, D13, D14, D15)>;
>
> // Extended-size data register class
> def ER : RegisterClass<"TriCore", [i64], 32,
> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
> let SubRegClasses = [(DR sub_even, sub_odd)];
> }
>
> And the DX and EX registers are defined this way:
The regclasses look fine... So, you need to figure out why
getRepRegClassFor() returns NULL in this case.
Side note: you can autogenerate register names :)
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mec...
2012 Jul 18
1
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
...o use a pattern that replaces 64bit-constants by tow
INSERT_SUBREG-nodes. I ended up having the following pattern:
def : Pat<(i64 imm:$imm),
(INSERT_SUBREG
(INSERT_SUBREG
(i64 (IMPLICIT_DEF)),
(i32 (LO32 imm:$imm)),
sub_even),
(i32 (HI32 imm:$imm)),
sub_odd)>;
OK, this leaves a DAG where all i64-Constant-nodes are replaced by to
nested INSERT_SUBREG-nodes, but how do I get rid of that
INSERT_SUBREG-stuff. Do I have to lower it separately? Should there be
some magic that eliminates those nodes for me?
Maybe, I just have to make clear that (LO32 im...
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
> This isn't really my area of expertise, but I think you're messing up
> your RegisterClass definition. Look at how ARM defines DTriple.
DTriple is untyped :) , because we do not have any valut type which
defines 3xi64.
However, the paired register needs to have type.
Fabian, what are the definitions of ER and DR register classes?
--
With best regards, Anton Korobeynikov
Faculty
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
..., D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15)>;
// Extended-size data register class
def ER : RegisterClass<"TriCore", [i64], 32,
(add E0, E2, E4, E6, E8, E10, E12, E14)> {
let SubRegClasses = [(DR sub_even, sub_odd)];
}
And the DX and EX registers are defined this way:
def D0 : TriCoreReg<0, "d0">, DwarfRegNum<[0]>;
...
def D15 : TriCoreReg<15, "d15">, DwarfRegNum<[15]>;
def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]>, DwarfRegNum<[32...
2012 Aug 22
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
..., D11, D12, D13, D14, D15)>;
>>>
>>> // Extended-size data register class
>>> def ER : RegisterClass<"TriCore", [i64], 32,
>>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>>> let SubRegClasses = [(DR sub_even, sub_odd)];
>>> }
>>>
>>> And the DX and EX registers are defined this way:
>> The regclasses look fine... So, you need to figure out why
>> getRepRegClassFor() returns NULL in this case.
> Well, that's rather easy :-) The register class is not registered in
>...
2012 Mar 21
4
[LLVMdev] apparent mistake in several ports register td file ???
...tring n> : SparcReg<n> {
let Num = num;
}
// Rd - Slots in the FP register file for 64-bit floating-point values.
class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
let Num = num;
let SubRegs = subregs;
let SubRegIndices = [sub_even, sub_odd];
let CoveredBySubRegs = 1;
}
......
// Mips CPU Registers
class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
let Num = num;
}
2012 Aug 22
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...D8, D9, D10, D11, D12, D13, D14, D15)>;
>>
>> // Extended-size data register class
>> def ER : RegisterClass<"TriCore", [i64], 32,
>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>> let SubRegClasses = [(DR sub_even, sub_odd)];
>> }
>>
>> And the DX and EX registers are defined this way:
> The regclasses look fine... So, you need to figure out why
> getRepRegClassFor() returns NULL in this case.
Well, that's rather easy :-) The register class is not registered in
the constructor of TriCoreT...
2012 Mar 23
0
[LLVMdev] apparent mistake in several ports register td file ???
...let Num = num;
> }
> // Rd - Slots in the FP register file for 64-bit floating-point values.
> class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
> let Num = num;
> let SubRegs = subregs;
> let SubRegIndices = [sub_even, sub_odd];
> let CoveredBySubRegs = 1;
> }
>
> ......
> // Mips CPU Registers
> class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
> let Num = num;
> }
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev...
2012 Aug 23
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
..., D15)>;
>>>>
>>>> // Extended-size data register class
>>>> def ER : RegisterClass<"TriCore", [i64], 32,
>>>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>>>> let SubRegClasses = [(DR sub_even, sub_odd)];
>>>> }
>>>>
>>>> And the DX and EX registers are defined this way:
>>>
>>> The regclasses look fine... So, you need to figure out why
>>> getRepRegClassFor() returns NULL in this case.
>>
>> Well, that's rather easy :...
2012 Aug 23
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...t;>>
>>>>> // Extended-size data register class
>>>>> def ER : RegisterClass<"TriCore", [i64], 32,
>>>>> (add E0, E2, E4, E6, E8, E10, E12, E14)> {
>>>>> let SubRegClasses = [(DR sub_even, sub_odd)];
>>>>> }
>>>>>
>>>>> And the DX and EX registers are defined this way:
>>>> The regclasses look fine... So, you need to figure out why
>>>> getRepRegClassFor() returns NULL in this case.
>>> Well, that's rather easy...
2012 Jul 12
0
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
On Thu, Jul 12, 2012 at 01:22:39PM +0200, Fabian Scheler wrote:
> Hi Micah,
>
> > We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
> >
> > What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
>
> thanks for your hint. Unfortunately, I didn't find any
2012 Jul 12
2
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
Hi Micah,
> We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
>
> What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
thanks for your hint. Unfortunately, I didn't find any time to work on
my problem in the meantime as I was busy preparing lectures. However,
the summer