search for: sub_32

...2, 0; GPR64:%vreg17 LS64_STR %vreg17<kill>, <fi#-2>, 0; mem:ST8[FixedStack-2](align=16) GPR64:%vreg17 %vreg19<def> = IMPLICIT_DEF; GPR64:%vreg19 %vreg20<def> = IMPLICIT_DEF; GPR32:%vreg20 %vreg18<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg20<kill>, sub_32; GPR64:%vreg18,%vreg19 GPR32:%vreg20 %X0<def> = COPY %vreg18; GPR64:%vreg18 %X1<def> = COPY %vreg18; GPR64:%vreg18 %X2<def> = COPY %vreg18; GPR64:%vreg18 %X3<def> = COPY %vreg18; GPR64:%vreg18 %X4<def> = COPY %vreg18; GPR64:%vreg18 %X5<def> = COPY %vreg18;...

...(add (mulB<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 1)), (mulBz<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))), (EXTRACT_SUBREG (i64 (DOT (DUPv2i32gpr WZR), (v8i8 (LD1Onev8b GPR64sp:$Rn)), (v8i8 (LD1Onev8b GPR64sp:$Rm)))), sub_32)>, Requires<[HasDotProd]>; def : DotProductI32<SDOTv8i8, sextloadi8>; def : DotProductI32<UDOTv8i8, zextloadi8>; Then when I extended it to 8 element vectors, the time spent by tblgen exploded: from under 7 seconds (on A-72) on the AArch64 td files and the above patch to...

...that, I can't seem to get RA to split the following: > > 1 BB#0: derived from LLVM BB %entry > 2 Live Ins: %X3 > 3 %vreg15<def> = COPY %X3; G8RC:%vreg15 > 4 %vreg4<def> = CMPLDI %vreg15, 0; CRRC:%vreg4 G8RC:%vreg15 > 5 %vreg11:sub_32<def,read-undef> = LI 0; G8RC:%vreg11 > 6 BCC 68, %vreg4, <BB#1>; CRRC:%vreg4 > 7 Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) > BB#1(0x50000000 / 0x80000000 = 62.50%) > 8 > 9 BB#4: > 10 Predecessors according to CFG: BB#0...

...ded). However, despite all of that, I can't seem to get RA to split the following: 1 BB#0: derived from LLVM BB %entry 2 Live Ins: %X3 3 %vreg15<def> = COPY %X3; G8RC:%vreg15 4 %vreg4<def> = CMPLDI %vreg15, 0; CRRC:%vreg4 G8RC:%vreg15 5 %vreg11:sub_32<def,read-undef> = LI 0; G8RC:%vreg11 6 BCC 68, %vreg4, <BB#1>; CRRC:%vreg4 7 Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) BB#1(0x50000000 / 0x80000000 = 62.50%) 8 9 BB#4: 10 Predecessors according to CFG: BB#0 11 B <BB#3> 1...

...g/viewvc/llvm-project?view=revision&revision=235869) is the cause of this regression. The problem is these three definitions: // Bypass trunc nodes for bitwise ops. def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))), (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>; def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))), (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))), (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; They're cor...

I'm trying to fix a bug in the PowerPC SPE backend that prevents a bunch of FreeBSD ports from building, including gtk20. The attached file, generated from the following C source, triggers the "Def == PreviousDef" assertion in isNopCopy(): typedef float a; typedef struct { a b, c; } complex; d(complex *e, complex *h) { double f = h->c, g = h->b; i(g); e->c = g *

...as far as RA is concerned, this is a "real" operation (a binary OR > which truncates the result to 32-bits (from 64-bit inputs)). In > effect, however, this is just a self copy. > > How can I fix this? def : Pat<(i32 (trunc G8RC:$in)), (EXTRACT_SUBREG G8RC:$in, sub_32)>; This exposes the copies to the register coalescer and VirtRegMap::rewrite() which eliminates identity copies. You can probably lose the OR8To4 pseudo after that. I assume there will be no problems with 32-bit instructions using the low part of 64-bit registers without clearing the high part...

.../BPF/BPFRegisterInfo.td > +++ b/lib/Target/BPF/BPFRegisterInfo.td > @@ -11,31 +11,63 @@ > // Declarations that describe the BPF register file > //===----------------------------------------------------------------------===// > > +let Namespace = "BPF" in { > + def sub_32 : SubRegIndex<32>; > +} > + > +class Wi<bits<16> Enc, string n> : Register<n> { > + let HWEncoding = Enc; > + let Namespace = "BPF"; > +} > + > // Registers are identified with 4-bit ID numbers. > // Ri - 64-bit integer registers >...

Hi, I have tagged the 3.6.1-rc1 so testing can begin. We can always use more testers, so if you are interested in helping, let me know. Instructions for validating an LLVM release can be found here: http://llvm.org/docs/ReleaseProcess.html Reminder: We are using 3.6.0 as our baseline for regression testing. Thanks, Tom

Hi all, I am currently working on AMDGPU inline assembly and encountered problem with naming clobber registers in asm constraints. It looks like by default LLVM tries to match register specified in constraint to register name of register definition in .td file but not to the AsmName for this register. For example if we have register definition: def MYReg0 : Register<"r0", 0>;

On Thu, 07 Jun 2012 10:34:03 +0200 Ivan Llopard <ivanllopard at gmail.com> wrote: > Hi Hal, > > On 07/06/2012 09:57, Chandler Carruth wrote: > > On Wed, Jun 6, 2012 at 10:37 PM, Hal Finkel <hfinkel at anl.gov > > <mailto:hfinkel at anl.gov>> wrote: > > > > I am working on cleaning up some PPC code generation. Two > > questions: >

Hi Hal, On 07/06/2012 09:57, Chandler Carruth wrote: > On Wed, Jun 6, 2012 at 10:37 PM, Hal Finkel <hfinkel at anl.gov > <mailto:hfinkel at anl.gov>> wrote: > > I am working on cleaning up some PPC code generation. Two questions: > > 1. Which pass is responsible for cleaning up self-moves: > 0x00000000100057c0 <+208>: mr r3,r3 > and