Displaying 5 results from an estimated 5 matches for "stwrr".
Did you mean:
strr
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
...def> = COPY %vreg0; PTRREGS:%vreg2 DREGS:%vreg0
%vreg1<def> = LDWRd %vreg2; mem:LD2[%a](align=1)(tbaa=!"int")
DLDREGS:%vreg1 PTRREGS:%vreg2
%vreg3<def> = ANDIWRdK %vreg1, 255; DLDREGS:%vreg3,%vreg1
%vreg5<def> = COPY %vreg0; PTRREGS:%vreg5 DREGS:%vreg0
STWRr %vreg5, %vreg3<kill>; mem:ST2[%a](align=1)(tbaa=!"int")
PTRREGS:%vreg5 DLDREGS:%vreg3
RET
>From above, the 3rd COPY instruction is redundant since it does exactly the
same thing as the second COPY instruction, so the stw (store) instr should
take %vreg2 instead of %vreg5. Af...
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...; PTRREGS:%vreg5
48L %vreg6<def> = LDWRd %vreg5<kill>;
mem:LD2[%a](align=1)(tbaa=!"int") DLDREGS:%vreg6 PTRREGS:%vreg5
80L %vreg6<def> = ANDIWRdK %vreg6, 255; DLDREGS:%vreg6
96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
112L STWRr %vreg8<kill>, %vreg6<kill>;
mem:ST2[%a](align=1)(tbaa=!"int") PTRREGS:%vreg8 DLDREGS:%vreg6
128L RET
What i see is the first copy getting coalesced so vreg0 goes away, and when
it tries and succeeds to coalesce vreg4 with vreg6 it kills vreg5 dont know
why. Because of...
2011 Mar 28
0
[LLVMdev] Possible missed optimization?
...; 48L %vreg6<def> = LDWRd %vreg5<kill>; mem:LD2[%a](align=1)(tbaa=!"int") DLDREGS:%vreg6 PTRREGS:%vreg5
> 80L %vreg6<def> = ANDIWRdK %vreg6, 255; DLDREGS:%vreg6
> 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
> 112L STWRr %vreg8<kill>, %vreg6<kill>; mem:ST2[%a](align=1)(tbaa=!"int") PTRREGS:%vreg8 DLDREGS:%vreg6
> 128L RET
>
> What i see is the first copy getting coalesced so vreg0 goes away, and when it tries and succeeds to coalesce vreg4 with vreg6 it kills vreg5 dont know w...
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 26, 2011, at 1:04 PM, Borja Ferrer wrote:
> Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
>
> DREGS: R31R30, R29R28 down to R1R0 (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
> PTRREGS:
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other