search for: strd

NIST maintains a repository of Statistical Reference Datasets at http://www.itl.nist.gov/div898/strd/. I have been working through the datasets to compare R's results to their references with the hope that if all works well, this could become a validation package. All the linear regression datasets give results with some degree of accuracy except one. The NIST model includes 11 parameters,...

...So I nominate it... but leave it to others to say whether it's really "qualified" to be nominated. ---- "The idea that the Excel solver "has a good reputation for being fast and accurate" does not withstand an examination of the Excel solver's ability to solve the StRD nls test problems. ... Excel solver does have the virtue that it will always produce an answer, albeit one with zero accurate digits." --- I also leave it to others to modify what is excerpted if appropriate. Cheers, Bert On Wed, Feb 20, 2013 at 7:58 AM, Bruce McCullough <bdmccullough...

The idea that the Excel solver "has a good reputation for being fast and accurate" does not withstand an examination of the Excel solver's ability to solve the StRD nls test problems. Solver's ability is abysmal. 13 of 27 "answers" have zero accurate digits, and three more have fewer than two accurate digits -- and this is after tuning the solver to get a good answer. For details see B. D. McCullough and Berry Wilson "On the Accuracy...

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all - As I progress in R I am trying to automate functions I would have normally farmed out to Excel, SPSS or Statistica. Single factor anova is one of them. For example, a dataset from NIST StRD (http://www.itl.nist.gov/div898/strd/anova/AtmWtAg.html) has two groups: 1 2 107.8681568 107.8681079 107.8681465 107.8681344 107.8681572 107.8681513 107.8681785 107.8681197 107.8681446 107.8681604 107.8681903 107.8681385 107.8681526 107.8681642 107.8681494 107.8681365...

...RM 'ldrd' double-load instruction. Unfortunately, some ARM hardware platforms (including all of Apple's) support misaligned accesses for single-register loads and stores ('ldr' and 'str' instructions), but not for double-register loads and stores ('ldrd' and 'strd' instructions.). On those platforms, the attached code triggers an address error when passed a misaligned address if it's compiled by LLVM with the optimizer enabled, but not if it's compiled by gcc, or by LLVM with the optimizer disabled. At a minimum, there should be an option to disa...

Dear Users! I encountered with some problem in data reading while I challenged R (and me too) in a validation point of view. In this issue, I tried to utilize some reference datasets ( http://www.itl.nist.gov/div898/strd/index.html). And the result departed a bit from my expectations. This dataset dedicated to challenge cancellation and accumulation errors (case SmLs07), that's why this uncommon look of txt file. Treatment Response 1 1000000000000.4 1 1000000000000.3 1...

...RM 'ldrd' double-load instruction. Unfortunately, some ARM hardware platforms (including all of Apple's) support misaligned accesses for single-register loads and stores ('ldr' and 'str' instructions), but not for double-register loads and stores ('ldrd' and 'strd' instructions.). > On those platforms, the attached code triggers an address error when passed a misaligned address if it's compiled by LLVM with the optimizer enabled, but not if it's compiled by gcc, or by LLVM with the optimizer disabled. > At a minimum, there should be an opti...

...RM 'ldrd' double-load instruction. Unfortunately, some ARM hardware platforms (including all of Apple's) support misaligned accesses for single-register loads and stores ('ldr' and 'str' instructions), but not for double-register loads and stores ('ldrd' and 'strd' instructions.). >> On those platforms, the attached code triggers an address error when passed a misaligned address if it's compiled by LLVM with the optimizer enabled, but not if it's compiled by gcc, or by LLVM with the optimizer disabled. >> At a minimum, there should be...

Hello, I am trying to test the precision of R on datasets from The Statistical Reference Datasets Project http://www.itl.nist.gov/div898/strd/index.html and I don't manage to understand how R is storing its results. For example, I calculate a mean on the michelso dataset (100 values) and find: > m=mean(michel) > m V1 299.8524 > print(m,digits=15) V1 299.8524 > print(m,digits=22) V1 29...

...t;r"(b)); Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Thus I believe the safest solution is to always force 64-bit operands into even/odd pairs for any inline asm. In other words, we shou...

On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: > One possible fix, which I have tested, is to look for the specific > instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in > addition to the 'H' modifier. However, there are probably other > creative ways in which inline asm might rely on the specific pairing. > Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able t...

...o a certain number > of decimal places on some benchmark calculations. I don't know of any references, but maybe you can somehow "verify the accuracy of R" by running some analysis with the "NIST Statistical Reference Datasets"; the URL is http://www.itl.nist.gov/div898/strd/ So maybe you can run the analyses mentioned there and say that R (hopefully) returned the correct results. Hope this helps, Roland ---------- This mail has been sent through the MPI for Demographic Rese...{{dropped}}

Hi people, I need to prove the good quality of numerical accuracy of R. Anyone knows a paper or anything else comparing R to other statistical softwares in terms of numerical accuracy. I've made a long search about that but I found nothing. Please help me!! Thanx, Talita Leite ------------------------------------------------- Este e-mail foi enviado pelo Webmail da UFAL IMP:

...le.com>> wrote: >>> >>> Hi James, >>> >>> I’m not too familiar with Sparc’s design here, but you may find it useful to have a look at how the ARM target deals with this sort of thing. In particular, the load/store optimization pass which can form the LDRD/STRD instructions among other things. >>> >>> -Jim >>> >>>> On Apr 2, 2015, at 11:43 AM, James Y Knight <jyknight at google.com <mailto:jyknight at google.com> <mailto:jyknight at google.com <mailto:jyknight at google.com>>> wrote: >&gt...

...d Cc: LLVM Dev; weimingz at codeaurora.org Subject: Re: Problems with 64-bit register operands of inline asm on ARM On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to have so...

...2] str r3, [fp, #-5] ..... What I want to do is to merge neighboring stores and loads. For example mov r3, #2 mov r2, #3 str r3, [fp, #-5] str r2, [fp, #-4] Can be converted to mov r3, #2 mov r2, #3 strd r2, [fp, #-4] But the main problem is that the offset for r3 in the snippet above was -3, not -5. Currently, i'm doing the following. During the pre-RA i'm creating a REG_SEQUENCE with the target class, assigning vregs in question as its subregs, and create a load/store inst for the seq...

...licon to support them. With Xcode's switch to LLVM, this deployed silicon has suddenly become off-limits because of a single overzealous optimization. The only possible workarounds are assembly code and turning the optimizer off altogether. It would be one thing if the optimizer generated ldrd/strd for 64-bit loads and stores only. But it actually goes as far as taking two separate 32-bit accesses and merging them into one silently-incompatible 64-bit access. These two accesses could be unrelated to one another in the context of the code at hand, and even syntactically distant. This introduc...

...gz at codeaurora.org > Subject: Re: Problems with 64-bit register operands of inline asm on ARM > > On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: > One possible fix, which I have tested, is to look for the specific > instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in > addition to the 'H' modifier. However, there are probably other > creative ways in which inline asm might rely on the specific pairing. > > Hi Mans, > > Either that method is ignoring an inline asm parser or there isn't one, but I agree, we...

...plfied in the codegen for the function @bar in the attached IR file: bar: push {r4, lr} sub sp, #12 (1) movw r2, :lower16:.L_MergedGlobals (1) movt r2, :upper16:.L_MergedGlobals ldm.w r2, {r0, r1, r3, r12, lr} ldrd r4, r2, [r2, #20] strd lr, r4, [sp] str r2, [sp, #8] (2) mov r2, r3 **** mov r3, r12 **** bl baz add sp, #12 pop {r4, pc} The two moves marked with **** are unnecessary. Especially the first, which could be removed simply by swapping...

...t; > What I want to do is to merge neighboring stores and loads. For example > mov r3, #2 > mov r2, #3 > str r3, [fp, #-5] > str r2, [fp, #-4] > Can be converted to > mov r3, #2 > mov r2, #3 > strd r2, [fp, #-4] > But the main problem is that the offset for r3 in the snippet above was > -3, not -5. > > Currently, i'm doing the following. During the pre-RA i'm creating a > REG_SEQUENCE with the target class, assigning vregs in question as its > subregs, and create...