search for: stores

...ion when it is passed a list of store instructions. With this patch, the command: opt -slp-vectorizer -debug -march=r600 -mcpu=redwood -o - vector-alloca.ll -S -slp-threshold=-20 Produces the following output and the program remains unchanged: ==== SLP: Analyzing blocks in vector. SLP: Found 5 stores to vectorize. SLP: Analyzing a store chain of length 4. SLP: Analyzing a store chain of length 4 SLP: Analyzing 4 stores at offset 0 SLP: Checking users of store i32 0, i32* %x. SLP: Checking users of store i32 1, i32* %y. SLP: Checking users of store i32 2, i32* %z. SLP: Checking users...

It is possible to ask DataLayout about getTypeSizeInBits and also getTypeStoreSize. And there is a table showing an example of what it could look like: /// Size examples: /// /// Type SizeInBits StoreSizeInBits AllocSizeInBits[*] /// ---- ---------- --------------- --------------- /// i1 1 8 8 /// i8...

...store i8 3, i8* %4, align 1 %5 = getelementptr inbounds i8* %0, i32 3 store i8 4, i8* %5, align 1 ret void This code also results in a single store. However, there is no guarantee that the input pointer is 32-bit aligned. x86_64 tolerates this, but the ABI mandates aligned loads and stores. My previous example guaranteed alignment, because I started with a pointer to a structure containing a member having 8-byte alignment, therefore we could infer the alignment of some of the stores. And checking the code in DAGCombiner.cpp indeed shows that all combined instructions have to have th...

...ook at a example as follows: typedef unsigned short int UV __attribute__((vector_size (8))); void test (UV *x, UV *y) { *x = *y / ((UV) { 4, 4, 4, 4 }); } The target does not support vector type so CodeGen tries to split and scalarize vector to legalize type. While legalizing vector type, the stores of each vector elements nodes are generated from 'DAGTypeLegalizer::SplitVecOp_STORE'. But the stores are not connected with chain. I guess it assumes each vector element's address is different. The each store is lowered to load and store nodes with high and low address but they are not...

...3 = getelementptr i32, i32* %1, i16 2 store i32 0, i32* %b03 %a04 = getelementptr i8, i8* %0, i16 3 store i8 0, i8* %a04 ; in the real case this also loads data %b04 = getelementptr i32, i32* %1, i16 3 store i32 0, i32* %b04 ret void } I expected LLVM to be able to coalesce the i8 stores to an i32 (or a number of i64 stores in my actual case). But it turns out it doesn't really do so. In postgres' current use the optimization pipeline doesn't contain SLP (mostly because enabling it via PassManagerBuilder isn't exposed to C). In that case optimization doesn't y...

...tions. With this patch, the command: > > opt -slp-vectorizer -debug -march=r600 -mcpu=redwood -o - vector-alloca.ll -S -slp-threshold=-20 > > Produces the following output and the program remains unchanged: > > ==== > > SLP: Analyzing blocks in vector. > SLP: Found 5 stores to vectorize. > SLP: Analyzing a store chain of length 4. > SLP: Analyzing a store chain of length 4 > SLP: Analyzing 4 stores at offset 0 > SLP: Checking users of store i32 0, i32* %x. > SLP: Checking users of store i32 1, i32* %y. > SLP: Checking users of store i32 2,...

Hi, I am looking for an elegant way to transform a vector into percentages of values that meet certain criteria. store<-c(1,1.4,3,1.1,0.3,0.6,4,5) # now I want to get the precentages of values # that fall into the categories <=M , >M & <=N , >N # let M <-.8 N <- 1.2 # In my real example I have many more of these cutoff-points # What I did is: out <- matrix(NA,1,3)

Hi, I haven't been able to reproduce this problem on a smaller test and the original source code is from another virtual machine's IR. What I found out was that 42 << 7 is actually DPSoRegImmFrm, defined in ARMInstrFormats.td. This format is not dealt with in the ARMCodeEmitter.cpp and that's the problem I'm facing. The triple I'm using is

Thanks Anton and Krzysztof! Here is the dump using the -debug flag. At this point I am not making much sense of this, would it be too much to ask if one of you could walk me through one of these lines? One thing that I didn't point out is that I never defined any separate floating point registers, not sure if this will pose any issue? Thanks again for your time! Jeff jeff at

...tructType* %0, i32 0, i32 2 store i8 3, i8* %4, align 2 %5 = getelementptr inbounds %UodStructType* %0, i32 0, i32 3 store i8 4, i8* %5, align 1 ret void } If I run this through opt -O3, it passes through unchanged. However, I would think that it would be profitable to combine the stores into a single instruction, e.g.: define void @test(%UodStructType*) { %2 = bitcast %UodStructType* %0 to i32* store i32 0x04030201, i32* %2, align 8 ret void } I don't see any optimization that would do this. Interestingly, if I store the same 8-bit constant in all four bytes, th...

Hello ferret users, I have a problem with ferret dropping stored fields in the index. Not all fields I want to store get stored, so they can be searched, but can''t be retrieved in a search. Index creation: INDEX = Index::Index.new(:path => ''/home/gregor/wisa/index'', :analyzer => Analysis::WhiteSpaceAnalyzer.new) SR =

...ariable between functions). > > Generally this seems to be handled by XYZISelDAGToDAG.cpp, which > converts an ISD::FrameIndex into an appropriate arithmetic instruction > that can offset from SP. That gets lowered to actual known offsets > later on, in exactly the same way loads and stores are. > > It's probably done in C++ rather than TableGen because the operands of > these resulting instructions often look pretty weird (for example a > TargetFrameIndex instead of a register). That's mostly speculation > though, I haven't tried to write a bare frameindex...

...04 > > > > ret void > > } > > > So, here we finally come to my question: Is it really expected that, > > unless largely independent optimizations (SLP in this case) happen to > > move instructions *within the same basic block* out of the way, these > > stores don't get coalesced? And then only if the either the > > optimization pipeline is run again, or if instruction selection can do > > so? > > > > > > On IRC Roman Lebedev pointed out https://reviews.llvm.org/D48725 which > > might address this indirectly. But...

...platform. > > > > masked_store(<42, 42>, Ptr, <true, false>) > > > > Does this write to the entier <2 x i64> object stored at Ptr or not? > > No. It writes one element. > Is this a statement about all of the existing hardware that supports masked stores, or about the desired semantics in your mind for the IR model? > > > Put another way, consider: > > > > thread A: > > ... > > masked_store(<42, 42>, Ptr, <true, false>) > > ... > > > > thread B: > > ... > > masked_store(&l...

...unsigned short int UV __attribute__((vector_size (8))); > > void test (UV *x, UV *y) { > *x = *y / ((UV) { 4, 4, 4, 4 }); > } > > The target does not support vector type so CodeGen tries to split and > scalarize vector to legalize type. While legalizing vector type, the > stores of each vector elements nodes are generated from > 'DAGTypeLegalizer::SplitVecOp_STORE'. But the stores are not connected > with chain. I guess it assumes each vector element's address is > different. The each store is lowered to load and store nodes with high > and low addr...

Hi everyone, I'm learning how to use LLVM API and JIT engine and I've come across with an issue I haven't been able to figure out. The problem I'm having is that the wrong float is being stored in a float global variable. The code snippet I use to generate the float value is as follow: llvm::Type* type = // initialize with the global variable type; std::string

Hi Hal, Hal Finkel via llvm-dev wrote: > Some questions: Do we allow stores to these locations at all? Only if I'd vote for disallowing stores to these locations, but if "stores allowed only if the value is the same" is helpful in some situation then I don't have specific reasons why that would be problematic. > the value is the same? Must any chang...

Hi Guillermo, I’m unable to reproduce the error you’re seeing with your bitcode input. “llc –mtriple armv7a-unknown-linux-gnueabi –O3” succeeds. What are you using to reproduce, and what version? Cheers, James From: Guillermo Perez [mailto:gaperez64 at gmail.com] Sent: 20 February 2012 11:32 To: James Molloy; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] ARM opcode format Hi, I haven't

Dear All, I currently have one of my transforms creating the following store instruction: store [65536 x i8] zeroinitializer, [65536 x i8]* %buf.i, align 16 ... which causes the SelectionDAG code to assert out: Assertion failed: (ResNo < NumValues && "Illegal result number!"), function getValueType, file /Users/criswell/src/llvm/include/llvm/CodeGen/SelectionDAGNodes.h,

...ress is not aligned 4. I am doing it with lowering store as follow: 1. make low and high address with alignment. 2. load 2 words from low and high address. 3. manipulate them with values to store according to alignment. 4. store 2 words modified to low and high address There could be independent stores with same target memory address because it makes and accesses low and high address with lowering. In order to keep the order between loads and stores, I have used chain and glue on the DAG but some passes have mixed it in machine instruction level. I am feeling above idea is not good... Do I ne...