search for: stored

Hi, I've been playing around with the SLPVectorizer trying to get it to vectorize this simple program: define void @vector(i32 addrspace(1)* %out, i32 %index) { entry: %0 = alloca [4 x i32] %x = getelementptr [4 x i32]* %0, i32 0, i32 0 %y = getelementptr [4 x i32]* %0, i32 0, i32 1 %z = getelementptr [4 x i32]* %0, i32 0, i32 2 %w = getelementptr [4 x i32]* %0, i32 0, i32 3

It is possible to ask DataLayout about getTypeSizeInBits and also getTypeStoreSize. And there is a table showing an example of what it could look like: /// Size examples: /// /// Type SizeInBits StoreSizeInBits AllocSizeInBits[*] /// ---- ---------- --------------- --------------- /// i1 1 8 8 /// i8 8 8

Hmm... found an interesting issue: Given: %2 = getelementptr inbounds %UodStructType* %0, i32 0, i32 0 store i8 1, i8* %2, align 8 %3 = getelementptr inbounds %UodStructType* %0, i32 0, i32 1 store i8 2, i8* %3, align 1 %4 = getelementptr inbounds %UodStructType* %0, i32 0, i32 2 store i8 3, i8* %4, align 2 %5 = getelementptr inbounds %UodStructType* %0, i32 0, i32 3

Hi Krzysztof, Thanks for response. The method is working almost of test cases which use load and store instructions connected with chain. There is other situation. Let's look at a example as follows: typedef unsigned short int UV __attribute__((vector_size (8))); void test (UV *x, UV *y) { *x = *y / ((UV) { 4, 4, 4, 4 }); } The target does not support vector type so CodeGen tries to

Hi, I have, in postres, a piece of IR that, after inlining and constant propagation boils (when cooked on really high heat) down to (also attached for your convenience): source_filename = "pg" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" define void @evalexpr_0_0(i8* align 8 noalias, i32* align 8 noalias) {

Hi Tom, Thanks for working on this. The SLP-vectorizer thinks that %X %Y %Z and %W alias, so it tries to perform 4 scalar store operations (which is a bad idea). We need to figure out why AA thinks that X and Y may alias. Maybe there is a problem with the code that uses AA. Thanks, Nadav On Oct 24, 2013, at 2:04 PM, Tom Stellard <tom at stellard.net> wrote: > Hi, > >

Hi, I am looking for an elegant way to transform a vector into percentages of values that meet certain criteria. store<-c(1,1.4,3,1.1,0.3,0.6,4,5) # now I want to get the precentages of values # that fall into the categories <=M , >M & <=N , >N # let M <-.8 N <- 1.2 # In my real example I have many more of these cutoff-points # What I did is: out <- matrix(NA,1,3)

Hi, I haven't been able to reproduce this problem on a smaller test and the original source code is from another virtual machine's IR. What I found out was that 42 << 7 is actually DPSoRegImmFrm, defined in ARMInstrFormats.td. This format is not dealt with in the ARMCodeEmitter.cpp and that's the problem I'm facing. The triple I'm using is

Thanks Anton and Krzysztof! Here is the dump using the -debug flag. At this point I am not making much sense of this, would it be too much to ask if one of you could walk me through one of these lines? One thing that I didn't point out is that I never defined any separate floating point registers, not sure if this will pose any issue? Thanks again for your time! Jeff jeff at

Consider the following: target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" %UodStructType = type { i8, i8, i8, i8, i32, i8* } define void @test(%UodStructType*) { %2 = getelementptr inbounds %UodStructType* %0, i32 0, i32 0 store i8 1, i8* %2, align 8 %3 = getelementptr inbounds %UodStructType* %0, i32 0, i32 1

Hello ferret users, I have a problem with ferret dropping stored fields in the index. Not all fields I want to store get stored, so they can be searched, but can''t be retrieved in a search. Index creation: INDEX = Index::Index.new(:path => ''/home/gregor/wisa/index'', :analyzer => Analysis::WhiteSpaceAn...

...ear? > > It comes from something like: > > %ptr = alloca i8 > %var = alloca i8* > store i8* %ptr, i8** %var > > and in general it's not possible to eliminate the combination. > Aha, thanks. > > 2. If not, how do I change it so that the operand being stored would be > first loaded into a register, and that register would be used instead? > > While the store is being selected LLVM will just treat the value being > stored as a generic pointer-width integer unless you have written a > specific pattern for storing a FrameIndex somewhere....

Andres: FWIW, codegen will do the merge if you turn on global alias analysis for it "-combiner-global-alias-analysis". That said, we should be able to do this merging earlier. -Nirav On Mon, Sep 10, 2018 at 8:33 PM, Andres Freund via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > On 2018-09-10 13:42:21 -0700, Andres Freund wrote: > > I have, in postres,

...mantics for a masked store? > > Specifically, let me suppose a simplified vector model of <2 x i64> on > > an i64-word-size platform. > > > > masked_store(<42, 42>, Ptr, <true, false>) > > > > Does this write to the entier <2 x i64> object stored at Ptr or not? > > No. It writes one element. > Is this a statement about all of the existing hardware that supports masked stores, or about the desired semantics in your mind for the IR model? > > > Put another way, consider: > > > > thread A: > > ... > &...

I'm not clear, but it sounds like maybe your issue is not just alignment, but that you have no 1/2-byte load or store operations at all on your target? Do you mean that to do any 2-byte store, even if it's naturally aligned, you need to load the 4-byte word that contains it, replace the low or high half as appropriate, and then use a 4-byte store to store back the modified value? On Fri,

Hi everyone, I'm learning how to use LLVM API and JIT engine and I've come across with an issue I haven't been able to figure out. The problem I'm having is that the wrong float is being stored in a float global variable. The code snippet I use to generate the float value is as follow: llvm::Type* type = // initialize with the global variable type; std::string real_value = // initialized with the float value from std input. ... return ConstantFP::get(type,real_val...

Hi Hal, Hal Finkel via llvm-dev wrote: > Some questions: Do we allow stores to these locations at all? Only if I'd vote for disallowing stores to these locations, but if "stores allowed only if the value is the same" is helpful in some situation then I don't have specific reasons why that would be problematic. > the value is the same? Must any change be observable to

Hi Guillermo, I’m unable to reproduce the error you’re seeing with your bitcode input. “llc –mtriple armv7a-unknown-linux-gnueabi –O3” succeeds. What are you using to reproduce, and what version? Cheers, James From: Guillermo Perez [mailto:gaperez64 at gmail.com] Sent: 20 February 2012 11:32 To: James Molloy; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] ARM opcode format Hi, I haven't

Dear All, I currently have one of my transforms creating the following store instruction: store [65536 x i8] zeroinitializer, [65536 x i8]* %buf.i, align 16 ... which causes the SelectionDAG code to assert out: Assertion failed: (ResNo < NumValues && "Illegal result number!"), function getValueType, file /Users/criswell/src/llvm/include/llvm/CodeGen/SelectionDAGNodes.h,

Hi All, I have a question about store with unaligned memory address. I am working on target which has only 4 byte aligned load and store instruction and I am generating 2 load and store instructions to store value on memory which the address is not aligned 4. I am doing it with lowering store as follow: 1. make low and high address with alignment. 2. load 2 words from low and high address.