Displaying 13 results from an estimated 13 matches for "store2".
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2016 Nov 17
2
Possible MemCpyOpt bug?
...orking on the fix. Suppose the following IR:
%T = type { i32, i32 }
define void @f(%T* %a, %T* %b, %T* %c, %T* %d) {
%val = load %T, %T* %a, !alias.scope !{!10}
; store1
; Aliases the load
store %T { i32 22, i32 22 }, %T* %b, !alias.scope !{!11}
; store2
; Aliases the store below and the load. No-alias with above store
store %T { i32 44, i32 44 }, %T* %c, !alias.scope !{!12},
!noalias !{!11}
; store3
; MCO wants to combine this store with the load into a memcpy
store %T %val, %T* %d, !alias.sco...
2013 Dec 16
2
[LLVMdev] Question about Pre-RA-schedule in LLVM3.3
...s sequence instructions would be executed with less stalls and cycles.
However, in the latest version of LLVM, the Pre-RA-sched builds a scheduling graph(original graph) which is shown following.
//original graph
----> data flow
====> control flow
load1 ----> store1 ====> load2 ----> store2 ====> load3 ----> store3
//end original graph
So, Pre-RA-sched is unable to schedule apart load/store instruction pair.
Due to LiveRange in the Register Allocation stage, all load/store instruction pair are allocated the same register.
If we change the control flow in the above original grap...
2013 Dec 21
0
[LLVMdev] Question about Pre-RA-schedule in LLVM3.3
...ould be executed with less stalls and cycles.
> However, in the latest version of LLVM, the Pre-RA-sched builds a scheduling graph(original graph) which is shown following.
> //original graph
> ----> data flow
> ====> control flow
> load1 ----> store1 ====> load2 ----> store2 ====> load3 ----> store3
> //end original graph
> So, Pre-RA-sched is unable to schedule apart load/store instruction pair.
> Due to LiveRange in the Register Allocation stage, all load/store instruction pair are allocated the same register.
>
> If we change the control flow i...
2010 Mar 10
1
R CMD check issue with soft-linked directory
...able to boot Hardy when I wish. I soft-linked my R
working area i.e.,
/home/john/Rstuff ----> /media/lnx804/home/john/Rstuff
I can still build packages fine, but get
john at nsrv-jaunty:~/jtest$ R CMD check minqa
* checking for working pdflatex ... OK
* using log directory '/media/store2/jn/test/minqa.Rcheck'
* using R version 2.10.1 (2009-12-14)
* using session charset: UTF-8
* checking for file 'minqa/DESCRIPTION' ... OK
* checking extension type ... Package
* this is package 'minqa' version '1.02'
* checking package name space information ... OK
* che...
2006 Jan 04
2
Error: Device 2049 (vbd) could not be connected. Backend device not found.
...d the debian31 image from
http://jailtime.org. Initially, i had some problems
and changed the configuration file a little. Here it
is now:
-----------
kernel = "/boot/vmlinuz-2.6-xenU"
memory = 256
name = "debian.3-1"
nics = 1
#dhcp = "dhcp"
disk =
[''file:/mnt/store2/xen/debian/debian31.img,sda1,w'']
root = "/dev/sda1"
-----------
However,
vakhos:/mnt/store2/xen/debian31# xm create -c
debian.3-1.xen.cfg
Using config file "debian.3-1.xen.cfg".
Error: Device 2049 (vbd) could not be connected.
Backend device not found.
Ideas? Thanks...
2013 Dec 15
3
[LLVMdev] Question about Pre-RA-schedule in LLVM3.3
...SDNode(load1 Instruction) and the second store1 SDNode.
Then in the register allocation step, the pair instruction are allocated same register.
However, if we build a schedule graph like the following:
I think that Pre-RA-sched has change to schedule apart load1 and store1, the same to load2 and store2.
Have someone considered building such a schedule graph?
Thank you very much if any suggestion.
-Haishan
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2013 Dec 15
0
[LLVMdev] Question about Pre-RA-schedule in LLVM3.3
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Haishan
> Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3
> My clang version is 3.3 and debug build.
> //test.c
> int a[6] = {1, 2, 3, 4, 5, 6}
> int main() {
> a[0] = a[5];
> a[1] = a[4];
> a[2] = a[5];
> }
> //end test.c
> Then test.dump is
2008 Nov 24
2
Indexes recovery failed
...o,
Was getting the following error repeatedly in my mail client (squirremail)
"error: connection dropped by IMAP server"
Looked at the logs for this user and found the following:
Nov 19 17:11:32 mink dovecot: IMAP(bobuser at maildom.com): broken sync
positions in index file
/virtual/store2/mail/s/bobuser_maildom.com/Maildir/dovecot.index
Nov 19 17:11:32 mink dovecot: IMAP(bobuser at maildom.com): fscking index
file /virtual/store2/mail/s/bobuser_maildom.com/Maildir/dovecot.index
Nov 19 17:11:32 mink dovecot: IMAP(bobuser at maildom.com): Fixed index
file /virtual/store2/mail/s/bobu...
2008 Aug 05
1
Corrupted transaction logs
...ul 12 11:25:51 mink dovecot: IMAP(user1 at domain1.net): Corrupted
transaction log file
/virtual/store1/mail/u/user1_domain1.net/Maildir/.Sent/dovecot.index.log:
Append with UID 925, but next_uid = 926
Jul 12 12:44:56 mink dovecot: IMAP(user2 at domain1.net): Corrupted
transaction log file
/virtual/store2/mail/u/user2_domain1.net/Maildir/.Trash/dovecot.index.log:
Append with UID 4927, but next_uid = 4931
Jul 12 12:45:19 mink dovecot: IMAP(user2 at domain1.net): Corrupted
transaction log file
/virtual/store2/mail/u/user2_domain1.net/Maildir/.Trash/dovecot.index.log:
Append with UID 4930, but next_uid...
2012 Apr 04
2
Using rsync to synchronize
...NED MESSAGE-----
Hash: SHA1
Hello,
I have been using rsync to backup our primary data stores. It works
fine. Here are the options I use for doing that:
rsync --recursive --links --times --dirs --stats --delete \
--itemize-changes --quiet --exclude-from=exclude-filename \
/data-store1/ /data-store2/
Recently I have had the need to actually synchronize the files
between two data stores. That is, whichever data store has the newest
timestamp updates the other data store.
What are some recommended ways for using rsync to synchronize two
data stores?
- --
James Moe
moe dot james at sohnen-...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...eStackTemporary(MVT::i64);
+ SDValue WordOff = DAG.getConstant(4, getPointerTy());
+ SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
+ getPointerTy(), StackSlot, WordOff);
+ SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op, StackSlot, NULL, 0);
+ SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
+ OffsetSlot, NULL, 0);
+ return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
}
std::pair<SDValue,SDValue> X86TargetLowering::
-FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
+FP_TO_INTHelp...