search for: stepvector

Displaying 20 results from an estimated 29 matches for "stepvector".

2018 Jun 05
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ith more certainty, move where it makes more sense. > Also, "iota" is the name Cray has traditionally used for this operation > as it is the mathematical name for the concept. It's also used by C++ > and go and so should be familiar to many people. That sounds better, but stepvector is more than C++'s iota and it's just a plain scalar evolution sequence like {start, op, step}. In C++'s iota (AFAICS), the step is always 1. Anyway, I don't mind any name, really. Whatever is more mnemonic. > ;; Create sequence for scalable vector > %stepvector = call &l...
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...the same manner as fixed-length vectors for a constant zero > splat. This can then be combined with `insertelement` and `shufflevector` > to create arbitrary value splats in the same manner as fixed-length vectors. > > For constants consisting of a sequence of values, an experimental `stepvector` > intrinsic has been added to represent a simple constant of the form > `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new > start can be added, and changing the step requires multiplying by a splat. > > Fixed-Length Code > ----------------- > `...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...stant can be used in the same manner as fixed-length vectors for a constant zero splat. This can then be combined with `insertelement` and `shufflevector` to create arbitrary value splats in the same manner as fixed-length vectors. For constants consisting of a sequence of values, an experimental `stepvector` intrinsic has been added to represent a simple constant of the form `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new start can be added, and changing the step requires multiplying by a splat. Fixed-Length Code ----------------- `` ;; Splat a value %insert = in...
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...n the same manner as fixed-length vectors for a constant zero > splat. This can then be combined with `insertelement` and `shufflevector` > to create arbitrary value splats in the same manner as fixed-length vectors. > > For constants consisting of a sequence of values, an experimental `stepvector` > intrinsic has been added to represent a simple constant of the form > `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new > start can be added, and changing the step requires multiplying by a splat. > > Fixed-Length Code > ----------------- > ``...
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...stant can be used in the same manner as fixed-length vectors for a constant zero splat. This can then be combined with `insertelement` and `shufflevector` to create arbitrary value splats in the same manner as fixed-length vectors. For constants consisting of a sequence of values, an experimental `stepvector` intrinsic has been added to represent a simple constant of the form `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new start can be added, and changing the step requires multiplying by a splat. Fixed-Length Code ----------------- `` ;; Splat a value %insert = in...
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...gt; > splat. This can then be combined with `insertelement` and > `shufflevector` > > to create arbitrary value splats in the same manner as > fixed-length vectors. > > > > For constants consisting of a sequence of values, an > experimental `stepvector` > > intrinsic has been added to represent a simple constant of the form > > `<0, 1, 2... num_elems-1>`. To change the starting value a splat > of the new > > start can be added, and changing the step requires multiplying > by a splat. > >...
2019 Jul 16
4
Scalable Vector Types in IR - Next Steps?
Hi Alex, We've only recently managed to get the core scalable vector IR type into the codebase (so it will be present in 9.0); that allows you to write IR with scalable vector types, but there's no backend able to generate code for it yet, and as you mention no support for stepvector (or vscale). Arm will start upstreaming those soon. -Graham > On 13 Jul 2019, at 14:32, Alex Susu via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hello. > I am very interested in adding scalable vector support in my LLVM 8.0 compiler for the Connex SIMD research process...
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...stant can be used in the same manner as fixed-length vectors for a constant zero splat. This can then be combined with `insertelement` and `shufflevector` to create arbitrary value splats in the same manner as fixed-length vectors. For constants consisting of a sequence of values, an experimental `stepvector` intrinsic has been added to represent a simple constant of the form `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new start can be added, and changing the step requires multiplying by a splat. Fixed-Length Code ----------------- `` ;; Splat a value %insert = in...
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...n the same manner as fixed-length vectors for a constant zero > splat. This can then be combined with `insertelement` and `shufflevector` > to create arbitrary value splats in the same manner as fixed-length vectors. > > For constants consisting of a sequence of values, an experimental `stepvector` > intrinsic has been added to represent a simple constant of the form > `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new > start can be added, and changing the step requires multiplying by a splat. > > Fixed-Length Code > ----------------- > ``...
2016 Nov 24
2
[RFC] Supporting ARM's SVE in LLVM
...eValue::get(Type *Ty); > ``` > > ### Example: > > The following shows how an induction variable would be incremented for a > scalable vector of type `<n x 4 x i32>`. > > ```llvm > %index.next = add nuw nsw i64 %index, mul (i64 vscale, i64 4) > ``` > > ## *stepvector* > > ### Syntax: > > > `stepvector` > > ### Overview: > > This complex constant represents the runtime value of a vector of > increasing > integers in the arithmetic series: > > > `<0, 1, 2, ... num_elements-1>` > > This is the basis for a scala...
2016 Nov 29
2
[RFC] Supporting ARM's SVE in LLVM
On Mon, Nov 28, 2016 at 7:37 AM Paul Walker via llvm-dev < llvm-dev at lists.llvm.org> wrote: > That is my intention with the stepvector patch ( > https://reviews.llvm.org/D27105). You can see that the interface is > common but for non-scalable vectors the result is its equivalent > ConstantVector. Once an agreed form is available > LoopVectorize::getStepVector can be converted to become compatible with > scalable v...
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...n the same manner as fixed-length vectors for a constant zero > splat. This can then be combined with `insertelement` and `shufflevector` > to create arbitrary value splats in the same manner as fixed-length vectors. > > For constants consisting of a sequence of values, an experimental `stepvector` > intrinsic has been added to represent a simple constant of the form > `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new > start can be added, and changing the step requires multiplying by a splat. > > Fixed-Length Code > ----------------- > ``...
2016 Nov 22
3
[RFC] Supporting ARM's SVE in LLVM
Hi Renato, Sorry for the delay in responding. We've been busy rethinking some of our changes after the feedback we've received thus far (particularly from the devmeeting). The incremental patches will use our revised design(which should be less invasive), and I'll be updating our document to match. On 16/11/2016, 12:46, "Renato Golin" <renato.golin at linaro.org>
2016 Nov 27
2
[RFC] Supporting ARM's SVE in LLVM
On 27 November 2016 at 16:51, Amara Emerson <amara.emerson at gmail.com> wrote: > There is nothing to stop other targets from using > stepvector/seriesvector. In fact for wide vector targets, often the IR > constant for representing a step vector is explicitly expressed as > <i32 0, i32 1, i32 2..> and so on (this gets really cumbersome when > your vector length is 512bits for example). That could be replaced by > a single...
2018 Jun 05
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...; other fundamental addressing operations are Instructions. We've tried it as both an instruction and as a 'Constant', and both work fine with ScalarEvolution. I have not yet tried it with the intrinsic. > >> For constants consisting of a sequence of values, an experimental `stepvector` >> intrinsic has been added to represent a simple constant of the form >> `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new >> start can be added, and changing the step requires multiplying by a splat. > > This is another case where an Instr...
2019 Mar 29
2
Scalable Vector Types in IR - Next Steps?
I had a phone conversation yesterday with Graham, Francesco, and Kristof. There is one more reason to go with the native type change: ARM has already written the code with the SV types, and they have patches ready to be reviewed and integrated in LLVM. As I don't want to stand in the way of getting SVE in LLVM as soon as possible, I will also support the integration of the existing patches
2017 Jun 07
2
[RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
...gt; value. When splitting, the linear order of elements would be preserved, so given a vector like <1, 2, 3, ... 2n> you would end up with <1, 2, ... n> and <n+1, n+2, ... 2n>. If you need a different arrangement, the shufflevector instruction can be used with appropriate use of stepvector and vscale to generate masks. The IR predicates for a given scalable vector (for select) just match the number of elements, e.g. <n x 8 x i1> for the <n x 8 x i32>, and would be split along with it during legalization. As you say, the main legal types for SVE are based around multiple...
2016 Nov 26
9
[RFC] Supporting ARM's SVE in LLVM
On 26 November 2016 at 11:49, Paul Walker <Paul.Walker at arm.com> wrote: > Related to this I want to push this and related conversations in a different direction. From the outset our approach to add SVE support to LLVM IR has been about solving the generic problem of vectorising for an unknown vector length and then extending this to support predication. With this in mind I would
2017 Jun 01
4
[RFC][SVE] Supporting Scalable Vector Architectures in LLVM IR (take 2)
...The `zeroinitializer` constant can be used as with fixed-length vectors for a constant zero splat. This can then be combined with `insertelement` and `shufflevector` to create arbitrary value splats in the same manner as fixed-length vectors. For constants consisting of a sequence of values, the `stepvector` constant is added to represent a simple constant of the form `<0, 1, 2... num_elems-1>`. To change the starting value a splat of the new start can be added, and changing the step requires multiplying by a splat. Alternatives Considered ----------------------- We have chosen to represent th...
2018 Jun 15
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...s type? How do I use half- and quarter-width vectors? Must I resort to predication? To split a <scalable 2 x double> in half, you'd use a shufflevector in much the same way you would for fixed-length vector types. e.g. `` %sv = call <scalable 1 x i32> @llvm.experimental.vector.stepvector.nxv1i32() %halfvec = shufflevector <scalable 2 x double> %fullvec, <scalable 2 x double> undef, <scalable 1 x i32> %sv `` You can't split it any further than a <scalable 1 x <ty>>, since there may only be one element in the actual hardware vector at runtime. The...