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...ange it in the register allocation pass or should i try it somewhere else?? example. lets say we have to add 2 registers addu rx ,ry ,rz there is a limitation that says that the two regs that will be added they can not have the same mod4 so we can add r1 , r2 but cannot add r1,r5. thanks Stavropoulos Nikos -- View this message in context: http://llvm.1065342.n5.nabble.com/Register-allocation-limitations-tp62967.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...can model your requirement in the *.td using RegisterClass as def SrcRegs : RegisterClass<"Src", [i32], 4, (add R0, R2, R4, R6 )>; def DstRegs : RegisterClass<"Dst", [i32], 4, (add R1, R3, R5, R7 )>; Thanks ~Umesh On Thu, Nov 7, 2013 at 8:25 PM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote: > Hi all. > > if there is limitation for the registers to be used together in an > instruction, should i try to change it in the register allocation pass > or should i try it somewhere else?? > > example. > > let...

...1065342.n5.nabble.com/PATCH-OpenCL-half-support-tt40041.html so the clang front-end could make IR with half. we created a target that has half float registers and tested on it. do you think it is a good idea to make a branch for it ?? or try to port it to llvm-3.2? thanks in advance Nikos Stavropoulos n.stavropoulos at think-silicon.com -- View this message in context: http://llvm.1065342.n5.nabble.com/llvm-3-1-with-native-half-support-alpha-version-tp54027.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Could you file a bug? On Wed, Feb 27, 2013 at 2:47 AM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote: > i have this code > > typedef long long L; > typedef integer I; > void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) > { > va_list select; > > va_start (select, p4); > > report( va_arg(selec...

i have this code typedef long long L; typedef integer I; void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) { va_list select; va_start (select, p4); report( va_arg(select,L) ); report( va_arg(select,I) ); report( va_arg(select,L) );

...GR32:$fd), (fadd (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; it makes and install correctly but when i ll try to write code to use this instruction there is no luck. Should i do something in ISelLowering.cpp or ISelDAGToDAG.cpp file? my backend is based on mips backend thanks in Advance, Stavropoulos Nikos -- View this message in context: http://llvm.1065342.n5.nabble.com/LLVMdev-Instruction-Implementation-tp56359.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...D::Lo 0x2349570 [ID=18] 0x2349570: i32 = TargetConstantPool<half 0x400A680000000000> 0 [TF=6] [ID=15] 0x2348e70: i32 = undef [ORD=1] [ID=3] So my question is As we are working on half float fp16 support in LLVM are there any plans to support it on the main trunk ? thanks Nikos Stavropoulos -- View this message in context: http://llvm.1065342.n5.nabble.com/Half-Float-fp16-Native-Support-tp50665.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

>I'm also a little worried that your pattern has fadd, but your C >source has a subtraction. :S i wrote it wrong the true implementation is def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fsub (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; I use some C,C++ code to test my backend. i use clang

i understand that is not right but this was the only way not to use the fadd for f32 "add.s" and use the "add.h" what ever i tried llvm moved everything to the float registers and did add.s and not the half add.h is there any trick to do that? i tried a lot but with no luck -- View this message in context:

Hi and thanks for answering llc works fine just does not selecting my instruction i ve uploaded .ll file how can i include this attribute "readonly" so i can see if changes the generated assembly? my code is very simple int main (){ float d, d1 ; d= 12.3; d1 = d - ceilf(d); return 0; } -- View this message in context: