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2011 May 25
2
[LLVMdev] Floating Point Register Allocation in X86 backend
Right. But there are 8 registers on the floating point stack from ST0 to ST7 and I think llvm is only using ST0 to ST6 in some code fragments. Could this be because of the assumption that X86::FP registers run from X86::FP0 to X86:FP6 ? --Aparna On Wed, May 25, 2011 at 2:28 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On May 25, 2011, at 11:09 AM, aparna kotha wrote: > > > Hi...
2012 May 02
2
Problem with 'nls' fitting logistic model (5PL)
...mple calibration data, representative of my experiment. Instrument soft had no problem fitting it: x <- structure(list(SPL = structure(c(1L, 1L, 2L, 2L, 3L, 3L, 4L, 4L, 5L, 5L, 6L, 6L, 7L, 7L), .Label = c("St1", "St2", "St3", "St4", "St5", "St6", "St7"), class = "factor"), MFI = c(10755.5, 9839, 5142.5, 4857, 1510.5, 1505, 502.5, 451, 215, 195.5, 58, 57, 15, 15), nom = c(206, 206, 125, 125, 68, 68, 38, 38, 24, 24, 13, 13, 6.5, 6.5), weights = c(0.0013946353028683, 0.00152454517735542, 0.00291686922702965, 0.003088...
2011 May 25
0
[LLVMdev] Floating Point Register Allocation in X86 backend
On May 25, 2011, at 12:08 PM, aparna kotha wrote: > Right. But there are 8 registers on the floating point stack from ST0 to ST7 and I think llvm is only using ST0 to ST6 in some code fragments. Could this be because of the assumption that X86::FP registers run from X86::FP0 to X86:FP6 ? Yes. My guess it that the code converting from FP to ST registers sometimes needs the extra stack slot. /jakob
2012 Jan 05
0
[LLVMdev] Spilling of partly (un)defined registers
...;kill>, %vreg59<imp-def>; aN40_0_7:%vreg59 Due to high register pressure vreg59 is spilled **** Local spiller rewriting MBB '': %vreg59:hi24<def,undef> = COPY %a1_gh<kill>, %vreg59<imp-def>; aN40_0_7:%vreg59 Store: Store40FI %a1_40<kill>,<fi#0>; mem:ST6[FixedStack0](align=2) And now the verifier complains: *** Bad machine code: Using an undefined physical register *** - function: accumconv - basic block: 0x97baae0 (BB#0) - instruction: Store40FI %a1_40<kill>,<fi#0>; mem:ST6[FixedStack0](align=2) - operand 0: %a1_40<kill> LLVM E...
2002 Dec 14
2
Nasty ext3 errors 2.4.18
...ote is that there was a panic on kswapd a number of hours earlier - but I've seen these on other systems running 2.4.18 and they don't seem to cause any problems (I think). As I've mentioned I've seen the same behavior before on other systems, the specs for all of them are: Abit ST6 Motherboard with 1.2 Gig Celeron 2 x disks (varying sizes and makes) 128Meg Ram AGP Graphics Card Ethernet Bt848 capture cards (2-3 depending on customer) I'm really pulling my hair out - I don't know why they are doing this - these are all on customer sites (they never go wrong in the of...
2011 May 25
0
[LLVMdev] Floating Point Register Allocation in X86 backend
On May 25, 2011, at 11:09 AM, aparna kotha wrote: > Hi Guys, > > I was working on some floating point intensive benchmarks and realize that the floating point register allocation in llvm assumes that there are only 7 floating point registers in X86, whereas the hardware has 8. > > Line number > 00266 assert(Reg >= X86::FP0 && Reg <= X86::FP6 &&
2008 Jul 24
1
Missing SDLT600's
...x 5600 switch. I've installed the latest (v8.02.14) drivers from Qlogic for the HBA The issue I have is I am missing 2 of the 4 SDLT drives provided by the M1800 Library. The DX30 provides 6 drives, which are listed in dmesg and assigned /dev/st0->5. I would expect the SDLT's to be st6->10 but I only see up to st7 and dmesg only lists 2 Using the QLoigic SAN Surfer software all the LUN's/devices are visible to the host. FYI, I also have an old Sun220R connected to this same switch with a qlogic card; Solaris 9 has no trouble seeing all LUNs and devices. I've &quo...
2007 Feb 25
1
[LLVMdev] X86RegisterInfo.td
...Floating point stack registers (these are not allocatable by the // register allocator - the floating point stackifier is responsible // for transforming FPn allocations to STn registers) def RST : RegisterClass<"X86", [f64], 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { let MethodProtos = [{ iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ RSTClass::iterator RSTClass::allocation_order_end(const MachineFunction &MF) const { return begin(); } }]; } Is the "beg...
2011 May 25
2
[LLVMdev] Floating Point Register Allocation in X86 backend
Hi Guys, I was working on some floating point intensive benchmarks and realize that the floating point register allocation in llvm assumes that there are only 7 floating point registers in X86, whereas the hardware has 8. Line number 00266 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); of X86FloatingPoint.cpp. Is there any reason for
2009 Aug 20
0
No subject
...KbN/ceH C/FZt88X8WpV/oE+8OtEkyAWiXMlZp4OjTDSAR7pq8Lo+/pd8ijQl83DIL2Ppe/zIfT927L/ 5oeO7etmiL+ImWZRx8CBOIq8GxWJILw1R7nN5R6G83kSeE7WugvxzYuvstus3UXH2iJeL2sg 92ZjSSre+N70TZDEb1auEwdHR0fiwE4t6pyp+FsYfc1u8jEMff2teJ9HUxYebl6+0e31xSvZ 7XfNXztp6DjlWpbOMjuumiaXwlc3yhfeQvzS+6WTNm9086cXeLH+2O12O4dXyvmaglVQ9so8 st6+0WEmfxWv9E/9Ud/oQHxSgRtGJ0cTYbrWVB/4EIVu4sTpkfRsfeR3O0hmthMnkYpSlfga hN+C1ZnlQxe6WjoYz5L5dP3ct8kiLU92PkbfU6t01M3tWMdVbl6nwMMN1SJzdf7lgVh89a6v 05jeWB8zq8+oZX3M/dZn9Fj1GT5PfYaPVR/reepj7b8+OT/m8/BjPlb7DJ6nfQb7q0/aIb9J O+SsPv03Rs9Yr096wnp9Zvq/e/XJOuhybYq++n5tjOV/q/r0G+qTHVOLTib8apFls2H0WsxV fBW6Qqcur8Z...
2002 Nov 08
2
2.4.18 ext3 problems
...54 24 28 8b 42 04 48 8b 4c 24 28 89 41 04 That finally caused the thread that was running to lock solid and the machine had to be power-cycled. Sorry I can't put the oops through ksymoops - opportunity lost. The system is running stock 2.4.18 build patched for lm-sensors Hardware is: Abit ST6 Motherboard + 256Meg + 1.2Gig Celeron 2x80 gig harddisks (make unknown !) 2xbttv capture cards 1xnetgear ethernet card The machine normally runs at around 40% idle, but is doing lot of disk writes, essentially its capturing video and writing it to disk (into 2 large partitions, 50 gig each) and it...
2014 Jul 25
0
Wine release 1.7.23
...leak in programs/wineconsole/registry.c 36314 valgrind shows a leak in psapi/tests/psapi_main.c 36512 client_rzrq.exe from AnXin crash when using the new style interface. 36545 REAPER 4.x crashes on exit 36601 valgrind shows a definite leak in wininet/tests/internet.c 36723 SolidEdge ST6 crashes on startup, needs bcrypt.dll.BCryptCloseAlgorithmProvider 36731 Runes of Magic 'ClientUpdater.exe' crashes after a number of update cycles (mshtml environment setup contains stack buffer overflow) 36741 Windows Live Writer 14.0.x fails to detect blog settings (HTMLMetaElement_...
2004 Aug 06
0
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...50 8SDX SIS 645/Socket 478/FSB 400/DMA 100/AGP 4X/CT5880/ATX 350 Éý¼¼ BL7-Raid Intel 845/ATX/Socket 478/FSB 133MHz/DMA 100/AGP 4X/AC97/Raid 420 BD7-Raid Intel 845D/Socket 478/ FSB 400/ATA100/AC97/ATX/AGP 4X/RAID 490 BD7II Intel 845E/Socket478/FSB533/DMA 100/AGP4X/AC97/10M/100M Lan 460 ST6-Raid Intel 815EPT/Socket 370/AGP 4X/DMA 100/AC97/Raid/ATX 390 KX7333R VIA KT333/Socket A/ATA 133/AGP 4X/Raid/ATX 500 KR7A VIA KT266A/Socket A/FSB266/ATA133/AGP 4X/ATX 460 KR7A-Raid VIA KT266A/Socket A/FSB 266/ATA133/AGP 4X/ATX 500 VP6 VIA 694X+686B/ATX/Socket370/FSB 133MHz/DMA100/AGP4X...
2010 Jun 21
2
[LLVMdev] MC: Object file specific parsing
....getLoc(), "expected stack index"); switch (IntTok.getIntVal()) { case 0: RegNo = X86::ST0; break; case 1: RegNo = X86::ST1; break; @@ -401,30 +463,30 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo, case 5: RegNo = X86::ST5; break; case 6: RegNo = X86::ST6; break; case 7: RegNo = X86::ST7; break; - default: return Error(IntTok.getLoc(), "invalid stack index"); + default: return Parser->Error(IntTok.getLoc(), "invalid stack index"); } - if (getParser().Lex().isNot(AsmToken::RParen)) - return Error(P...
2008 May 29
6
RE-export nfs mounted share
Hi Is there any way to re-export an nfs mounted directory? I am having three servers runnning on centos4.5 and i am trying to implement nfs share in an below manner [bcoz there is no alternative way for me to setup nfs share] HOST A--->>>EXPORTS /prod/data ------->>>HOST B HOST B ---->>MOUNTED ------>>> /prod/data-----UNDER---/PROD1 [working fine] HOST B
2009 Jul 23
1
[PATCH server] changes required for fedora rawhide inclusion.
...bK2i05c2*H1nf~hfE4NGEPWn12=asnzYC* zYfl?Ika_gW+%u;$$9*y-<HpvGGdUfyIEL*u`f=LQ?1R%dMcW;t&;C<}_>Gcr&)s|{ z&pC_a-aF1qY!>Npx?jjjeh3^W>rk?(qI;u>8c+Q~)%(KMO6c^J8BDK}VC(6?eXoX$ zJQtb`&aENoka)pwVI=@NK*Yb-H~9x^1M at WpsKb|$31UepLjZZ+5uA$uNjzfkd1&B4 zzK&{ptvNFEIeAR(-3gST6&XiC&e{`iarzW~_IMOy?y<U*J-~V4mx^6Au($#s3Hc(Y zl8+pi at v>-Ge)6hM#OjJL0Z7)PKvsu!&<FZ+ED1)pMiQ*vo>fxfqZ`Z50l0f8aGAgG z<kfz|^*dt*HZ&qHo6unnbHJJst9ym4V9auIk*UiQG7SMmEiUCv{?bqHC1$;J_uuf@ z4^!lXTd)@tV#GIYNt?c$AK09V at omA9fI82c{oOGK#Y8{*`V~IC1`2sxPa}mqPAu0e zphV802<BQqN(n...