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...ting point registers, not sure if this will pose any issue? Thanks again for your time! Jeff jeff at ubuntu:~/code$ llc -debug-only=isel dft_gf_msp.ll === main Initial selection DAG: BB#0 'main:entry' SelectionDAG has 18 nodes: t0: ch = EntryToken t4: ch = store<ST4[%retval]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32 t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>, undef:i32 t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>, FrameIndex:i32<3>, undef:i32 t1...

Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help

...like this may have something to do with the height. Can you explain how that is supposed to work? For the specific example: We start with the initial store... GPRC: 4 / 31 F4RC: 1 / 31 Examining Available: Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910, 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")> [ORD=94] [ID=102] Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60, 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97] Height 2: SU(92): 0x2c02860: ch = STFSX 0x2c02560, 0x2bf3910, 0x2c02160...

...turn address register) the whole code of print-machineinstrs are: # After PrologEpilogCodeInserter: # Machine code for function L_mpy_ls: Post SSA BB#0: derived from LLVM BB %0 Live Ins: %LR %S1 %S0 %SP<def> = ADDI %SP, -48 PROLOG_LABEL <MCSym=_tmp0> ST %LR<kill>, %SP, 44; mem:ST4[FixedStack0] ST %S1<kill>, %SP, 40; mem:ST4[FixedStack1] ST %S0<kill>, %SP, 36; mem:ST4[FixedStack2] PROLOG_LABEL <MCSym=_tmp1> %S0<def> = LD %SP, 48; mem:LD4[FixedStack-1](align=8) ST %S0, %SP, 0; mem:ST4[FixedStack-4](align=8) JSUB <ga:@extract_l>, <regmask>, %...

.... Can you > explain how that is supposed to work? > > For the specific example: We start with the initial store... > > GPRC: 4 / 31 > F4RC: 1 / 31 > > Examining Available: > Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910, > 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")> > [ORD=94] [ID=102] > > Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60, > 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97] > > Height 2: SU(92): 0x2c02860: ch = STFSX 0...

...upposed to work? >> >> For the specific example: We start with the initial store... >> >> GPRC: 4 / 31 >> F4RC: 1 / 31 >> >> Examining Available: >> Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910, >> 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")> >> [ORD=94] [ID=102] >> >> Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60, >> 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97] >> >> Height 2: SU(92):...

...e> 0x17d0fb0: <multiple use> 0x17f6680: i32 = Register %vreg0 [ORD=1] 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] 0x17f6880: <multiple use> 0x17f6a80: <multiple use> 0x17f6b80: ch = store 0x17d0fb0, 0x17f6780, 0x17f6880, 0x17f6a80<ST4[%a.addr]> [ORD=1] 0x17f6b80: <multiple use> 0x17f6b80: <multiple use> 0x17f6880: <multiple use> 0x17f6a80: <multiple use> 0x17f6c80: i32,ch = load 0x17f6b80, 0x17f6880, 0x17f6a80<LD4[%a.addr]> [ORD=2] 0...

On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > Here's my "thought experiment" (from PR11589): I have a bunch of > load-fadd-store chains to schedule. A store takes two cycles to clear > its last pipeline stage. The fadd takes longer to compute its result > (say 5 cycles), but can sustain a rate of 1 independent add per cycle. > As the scheduling is bottom-up, it

...llvm, using: $llc -debug test.bc where, test.c is like: int a, b, c, d, x; a = 3; b = 5; d = 4; x = 100; if ( a > b ) ...... And I got the machine code before register allocation: MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a] MOV32mi <fi#3>, 1, %reg0, 0, %reg0, 5; mem:ST4[%b] MOV32mi <fi#5>, 1, %reg0, 0, %reg0, 4; mem:ST4[%d] MOV32mi <fi#6>, 1, %reg0, 0, %reg0, 100; mem:ST4[%x] %reg16384<def> = MOV32rm <fi#3>, 1, %reg0, 0, %reg0; mem:LD4[%b] GR32:%reg1638...

...8520: <multiple use> 0x3eab3a0: <multiple use> 0x3eab4a8: i32 = add 0x3ea8520, 0x3eab3a0 [ORD=7] [ID=-3] 0x3ea4b08: <multiple use> 0x3ea45e0: <multiple use> 0x3eac5c0: ch = store 0x3ea4c10, 0x3eab4a8, 0x3ea4b08, 0x3ea45e0<ST4[%z]> [ORD=8] [ID=-3] 0x3ea4c10: <multiple use> 0x3ea7b70: <multiple use> 0x3eab190: <multiple use> 0x3eab298: i32 = add 0x3ea7b70, 0x3eab190 [ORD=7] [ID=-3] 0x3ea4b08: <multiple use> 0x3ea7120: <mult...

On Mon, 2011-12-19 at 22:14 -0800, Andrew Trick wrote: > On Dec 19, 2011, at 3:19 PM, Hal Finkel wrote: > > > On Mon, 2011-12-19 at 07:41 -0800, Andrew Trick wrote: > >> On Dec 19, 2011, at 6:51 AM, Hal Finkel <hfinkel at anl.gov> wrote: > >> > >>> On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote: > >>> Now, to generate the best

...row in a data frame (d), I am having troubles and getting errors using the code I have written. Below is a brief example of the code, any thought or suggestions would be great. Thank you for your time, Doug # Example Code: d <- data.frame(st1=c(1,2,3,4), st2=c(2,5,6,7), st3=c(5,5,NA,7), st4=c(6,5,7,8)) avg <- rep(NA,length(d[,1])) for (i in 1:length(d[,1])) { avg[i] = mean(d[i,1:4], na.rm=TRUE) } # Final Output wanted. st1 st2 st3 st4 avg 1 1 2 5 6 3.50 2 2 5 5 5 4.25 3 3 6 NA 7 5.33 4 4 7 7 8 6.50 -- --------------------------------- D...

...t) envir <- envir[!is.na(envir$Aeventexhumed), ] envir$QuadratEvent <- paste(envir$QuadratID, envir$Aeventexhumed, sep="") envir$QuadratEvent <- as.character(envir$QuadratEvent) ExDate <- Sector <- Quadrat <- Aeventexhumed <- NULL ST1 <- ST2 <- ST3 <- ST4 <- ST0 <- NULL Shells <- Hatchlings <- MaxHatch <- DeadHatch <- NULL Oldeggs <- TotalEggs <- QuadratEvent <- NULL for (q in unique(as.character(resp$QuadratEvent))) { s <- resp[as.character(resp$QuadratEvent) == q, ] ExDate <- c(ExDate, as.characte...

...et.rspa t0, TargetConstant:i16<392>, Constant:i32<64> t5: ch = llvm.clp.set.rspb t3, TargetConstant:i16<393>, Constant:i32<64> t8: ch = llvm.clp.set.rspsu t5, TargetConstant:i16<394>, Constant:i32<8> t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 t16: ch = store<Volatile ST4[@x2](tbaa=<0x3dbe418>)> t13, ConstantFP:f32<2.000000e+00>, GlobalAddress:i16<float* @x2> 0, undef:i16 t19: ch...

...MF->dump() # Machine code for function PointToHPoint: Frame Objects: fi#-1: size=48, align=8, fixed, at location [SP+8] fi#0: size=32, align=8, at location [SP] Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 BB#0: derived from LLVM BB %entry SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 The first two stores write the values in argument registers $6...

...;392>, > Constant:i32<64> > > t5: ch = llvm.clp.set.rspb t3, TargetConstant:i16<393>, Constant:i32<64> > >             t8: ch = llvm.clp.set.rspsu t5, TargetConstant:i16<394>, > Constant:i32<8> > >           t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 > >         t16: ch = store<Volatile ST4[@x2](tbaa=<0x3dbe418>)> t13, > ConstantFP:f32<2.000000e+00>, GlobalAddress:i16<float* @x2> 0,...

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

...y code generated for the function is: BB#0: derived from LLVM BB %entry %RSP<def> = SUB64ri8 %RSP, 24, %EFLAGS<imp-def,dead>; dbg:l8.cpp:1:1 PROLOG_LABEL <MCSym=.Ltmp0>; dbg:l8.cpp:1:1 DBG_VALUE %EDI, 0, !"arg1"; dbg:l8.cpp:3:1 MOV32mi %RSP, 1, %reg0, 20, %reg0, 21; mem:ST4[%X] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 16, %reg0, 22; mem:ST4[%Y] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 12, %reg0, 23; mem:ST4[%Z] dbg:l8.cpp:1:1 %EDI<def> = MOV32rm %RSP, 1, %reg0, 20, %reg0; mem:LD4[%X] dbg:l8.cpp:1:1 MOV32mr %RSP, 1, %reg0, 12, %reg0, %EDI; mem:ST4[%Z] dbg:l8.cpp:1:1...

...([18 x i8], [18 x i8]* @.str, i32 0, i32 0), i32 %2) ret i32 0 } Generated machine instructions (initial) BB#0: derived from LLVM BB %entry %vreg11<def> = MOVi32imm 6; GPR32:%vreg11 %vreg12<def> = MOVi32imm 5; GPR32:%vreg12 STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0] STRWui %vreg12, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg12 STRWui %vreg11, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg11 ................................. Best Nisal

...;392>, Constant:i32<64> > > t5: ch = llvm.clp.set.rspb t3, TargetConstant:i16<393>, > Constant:i32<64> > >             t8: ch = llvm.clp.set.rspsu t5, TargetConstant:i16<394>, > Constant:i32<8> > >           t13: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, > undef:i16 > >         t16: ch = store<Volatile ST4[@x2](tbaa=<0x3dbe418>)> t13, > ConstantFP:f32<2.000000e+00>, GlobalAddress:i16<float* @x2&g...