Displaying 2 results from an estimated 2 matches for "srlw".
Did you mean:
srl
2018 Dec 13
2
Dealing with information loss for widened integer operations at ISel time
...V32I. Rather
than adding 64-bit operations, it re-defines the operations as 64-bit and
introduces a small number of 'W' suffixed instructions such as ADDW, SLLW etc
to operate on 32-bit values.
There are some challenges though. Consider the variable-length shifts
introduced in RV64I. SLLW, SRLW, and SRAW operate on 32-bit values and produce
32-bit sign-extended results. They read only the lower 5 bits from the shift
amount. The following function should trivially resuslt in SRLW being
selected:
define signext i32 @sllw(i32 signext %a, i32 zeroext %b) {
%1 = shl i32 %a, %b...
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
On Thu, 13 Dec 2018 at 21:41, Friedman, Eli <efriedma at codeaurora.org> wrote:
>
> On 12/13/2018 6:25 AM, Alex Bradbury wrote:
> > There's also likely to be cases where you want to calculate the demanded bits
> > in order to determine if e.g. a W-suffixed instruction can be selected for
> > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match