Displaying 2 results from an estimated 2 matches for "srli".
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srl
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
...>;
This pattern would match but is incorrect in the general case (e.g. if
rs1 is 0xffffffff and rs2 is 0x1, the result will be sign-extended).:
def : Pat<(udiv (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)),
(DIVUW GPR:$rs1, GPR:$rs2)>;
So this function would generate:
slli a1, a1, 32
srli a1, a1, 32
slli a0, a0, 32
srli a0, a0, 32
divu a0, a0, a1
ret
Rather than a simple divuw. Obviously we can argue whether such cases
are likely to occur in real-world code (certainly this specific case
of aext function args/returns isn't going to happen for
clang-generated code), but it makes...
2018 Dec 13
2
Dealing with information loss for widened integer operations at ISel time
As previously discussed in an RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, the
RISC-V backend has i64 as the only legal integer type for the RV64 target.
Thanks to variable-sized register class support, this means there is no need
for duplication of either patterns or instruction definitions for RV32 and
RV64. It's worth noting that RV64I is a different base