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On Sep 5, 2014, at 10:21 AM, Juergen Ributzka <juergen at apple.com> wrote: > clearKillFlags seems a little "overkill" to me. In this case you could just simply transfer the value of the kill flag from the SrcReg to the DstReg. We are extending the live-range of SrcReg. I do not see how you could relate that to the kill flag of DstReg. Therefore, I still think, this is the right fix. -Quentin > > -Juergen > > On 09/05/14, Quentin Colombet <qcolombet at apple.com> wrote: >> &gt...

...0)); } unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { return 0; } void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) - .addReg(SrcReg, getKillRegState(KillSrc))); + // Need to check the arch. + MachineFunction &MF = *MBB.getParent(); + const ARMSubtarget &st = MF.getTarget().getS...

...ocumented. >> >> Can somebody explain what does it mean? > > Basically, it gives the target more information about the spill. In > particular, it specifies the register class to use for the copy. I'm still missing something. The 'storeRegToStackSlot' saves 'SrcReg' (already specified) to stack (which is not a register). So, what does this register class applies to? Examining RegAllocLocal.cpp suggests that the argument actually specifies the register class of the spilled virtual register. Can you give some examples how that information can be helpful?...

...tRegClass, but getRegClass is really supposed to take a register class enum value and get the register class object for it. It doesn't convert a register to a class. In fact there's not always a single or canonical class for a given register. What is the right way to do this? unsigned SrcReg = Reg + VA.getValNo(); unsigned DestReg = VA.getLocReg(); // Avoid a cross-class copy. This is very unlikely. if (!MRI.getRegClass(SrcReg)->contains(DestReg)) return false; ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists...

...ot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(1) .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); After this store I catch assertion failed: "Instruction not found in maps", because only last of this instruction added in Ins...

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hi, > I am using a cross compiler to compiler for the arm5 architecture. For this > architecture it is not allowed that a destination register is also used as source > register. > In 2007 a patch was discussed at the mailing list, however my compiler still is > producing this result. Does anyone know if this patch is actually applied? > > * I use the following arguments:

...achineSink.cpp index 7782001..261af54 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -157,6 +157,11 @@ bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI, DEBUG(dbgs() << "*** to: " << *MI); MRI->replaceRegWith(DstReg, SrcReg); MI->eraseFromParent(); + + // Conservatively, clear any kill flags, since it's possible that they are no + // longer correct. + MRI->clearKillFlags(SrcReg); + ++NumCoalesces; return true; } -- 2.1.0 From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu...

Hi, I am using a cross compiler to compiler for the arm5 architecture. For this architecture it is not allowed that a destination register is also used as source register. In 2007 a patch was discussed at the mailing list, however my compiler still is producing this result. Does anyone know if this patch is actually applied? * I use the following arguments: llvm-gcc -mfpu=vfp -mlittle-endian

...dded the code in ExpandPseudo to use the following pseudo instruction expansion: void MipsExpandPseudo::ExpandCopyF64(MachineBasicBlock& MBB, MachineBasicBlock::iterator I) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1); DebugLoc dl = I->getDebugLoc(); const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); BuildMI(MBB, I, dl, Dmfc1Tdd, DstReg).addReg(*SubReg); } Finally,...

...rary virtual register used in copy placement. For this setkill action it looks only in one instruction (last instruction for copyRegToReg) for virtual register with no use. My target has only one register and I can't do copyRegToReg in one instruction only. So I create two instructions (one:SrcReg to Stack , two:Stack to DestReg). The SrcReg here is the temporary virtual register (for PHI elimination) which should be setkill. However, the PHI Elimination pass looks only in last instruction (here: Stack to DestReg) for any NoUse register and does not find any. Therefore the intended setkill d...

...on for my > Target. This Target can store/load one byte (not all word) from FrameIndex. > If I need to store 16 bit register I will must to split it to two > instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion failed: "Instruction not found in > maps", because only last of t...

...se the following pseudo > instruction expansion: > > void MipsExpandPseudo::ExpandCopyF64(MachineBasicBlock& MBB, > MachineBasicBlock::iterator > I) { > unsigned DstReg = I->getOperand(0).getReg(); > unsigned SrcReg = I->getOperand(1).getReg(); > const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1); > > DebugLoc dl = I->getDebugLoc(); > const uint16_t* SubReg = > TM.getRegisterInfo()->getSubRegisters(SrcReg); > > BuildMI(MBB, I, dl, Dmfc1Tdd, DstReg)....

On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote: > I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.

...is wrong. I've managed to get around this by inserting a COPY in TailDuplication but I don't know what the proper fix is to this. In TailDuplicatePass::ProcessPHI: const TargetRegisterClass *RC = MRI->getRegClass(DefReg); + const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg); + + // If the register class of the PHI src is wider than the PHI def + // then we can't just use PHI src instead of PHI def in the cloned + // instruction. Instead we insert a copy, copying the PHI src to a + // register of the wanted register class. + if (!RC->hasSubClassEq(SrcRC))...

Hi LLVM, IRBuilder can fold constants (that behaviour can be controlled by Folder type). What do you think about optionally allow IRBuilder to eliminate no-op instructions like `add %a, 0` or `memcpy(%a, %b, 0)`? - Paweł -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150423/4f99a092/attachment.html>

I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer. The COPY instruction handles subreg operations with less

...l) > +++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Sun Jun 8 04:13:42 2014 > @@ -167,14 +167,9 @@ bool MipsFastISel::EmitStore(MVT VT, uns > // > // more cases will be handled here in following patches. > // > - if (VT == MVT::i32) > - EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); > - else if (VT == MVT::f32) > - EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset); > - else if (VT == MVT::f64) > - EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset); > - else > + if (VT != MVT::i32) > retur...

Hi, It looks like LiveIntervals::addIntervalsForSpills does not update all of the LiveIntervals infos quite correctly. In particular, if a live interval L is defined by Reg<-Reg copy instructions whose srcReg is later spilled by the addIntervalsForSpills() function, its VNInfo information is not updated in a proper way. It still points to the same MachineInstr as before, even though the MachineInstr was rewritten by addIntervalsForSpills(). This may lead to some problems during coalescing attempts after...

...get. This Target can store/load one byte (not all word) from > FrameIndex. If I need to store 16 bit register I will must to > split it to two instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion failed: "Instruction not found > in maps", beca...