search for: src0

...)) +#define OP00_LBL(op) define op(label) ureg_##op(ureg, label) +#define OP01_LBL(op) define op(src, label) ureg_##op(ureg, _src(src), label) +#define OP10(op) define op(dst) ureg_##op(ureg, dst) +#define OP11(op) define op(dst, src) ureg_##op(ureg, dst, _src(src)) +#define OP12(op) define op(dst, src0, src1) ureg_##op(ureg, dst, _src(src0), _src(src1)) +#define OP12_TEX(op) define op(dst, target, src0, src1) ureg_##op(ureg, dst, TGSI_TEXTURE_ CAT target, _src(src0), _src(src1)) +#define OP13(op) define op(dst, src0, src1, src2) ureg_##op(ureg, dst, _src(src0), _src(src1), _src(src2)) +#define OP...

...the machine instruction but sometimes if a vector_shuffle can only return LHS or RHS, it's removed/combined so that I cannot match vector_shuffle in the instruction selector. If the vector_shuffle is combined, I have to write the instruction selector like these: def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1), [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0), (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)] def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1), [sub REG:$src0, (vector_shuffle REG:$src1, R...

...tern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> { def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>; def _i16 : BinaryOp&l...

...tern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> { def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>; def _i16 : BinaryOp&l...

I have a tablegen string that I want to add a modifier to the registers that are being matched. For example a simple match on fneg: def FNEG : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins GPR:$src0), "mov $dst, $src0", [(set GPR:$dst, (fneg GPR:$src0))]>; I want to place a modifier directly after $src0 in the string so that no space is between the string and the matched register. I.e. I want to generate "mov $dst, $src0_neg", however, by putting the _neg r...

I do not have access to a subtraction routine, as it is considered add with negation on the second parameter, so I have this pattern: // integer subtraction // a - b ==> a + (-b) def ISUB : Pat<(sub GPRI32:$src0, GPRI32:$src1), (IADD GPRI32:$src0, (INEGATE GPRI32:$src1))>; I am attemping to do 64 bit integer shifts and using the following pattern: def LSHL : Pat<(shl GPRI64:$src0, GPRI32:$src1), (LCREATE (ISHL (LLO GPRI64:$src0), GPRI32:$src1), (IOR (ISHL (LHI...

...ring = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> { > def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>; >...

..., but I am still hitting another roadblock. I attempted what you suggested and it fixed that issue, but then it started giving a warning that there is an unknown node in the resulting pattern. // unsigned int: f64->i32 ==> f64->f32 + f32->i32 def : Pat<(i32 (fp_to_uint (f64 GPR:$src0))), (i32 (fp_to_uint (f32 (dp_to_fp (f64 GPR:$src0)))))>; 1>Building AMDil.td instruction selector implementation with tblgen 1>(fp_to_uint:i32 (dp_to_fp:f32 GPR:f64:$src0)) 1>f:\hq\main\sw\appeng\tools\hpc\opencl\llvm\win32\AMDIL\..\bin\Win32\De bug\TableGen.exe: Unknown...

I am not sure what you are looking to do. Please provide a mark up example. Evan On Oct 28, 2008, at 11:00 AM, Villmow, Micah wrote: > Is there currently a way to use a pattern inside of another pattern? > > Micah Villmow > Systems Engineer > Advanced Technology & Performance > Advanced Micro Devices Inc. > 4555 Great America Pkwy, > Santa Clara, CA. 95054 > P:

...; unsigned sampler_base:5; @@ -435,6 +443,7 @@ public: bool have_fma; bool use_shared_memory; bool has_tex_txf_lz; + unsigned precise; variable_storage *find_variable_storage(ir_variable *var); @@ -505,13 +514,29 @@ public: st_src_reg src0 = undef_src, st_src_reg src1 = undef_src, st_src_reg src2 = undef_src, - st_src_reg src3 = undef_src); + st_src_reg src3 = undef_src, +...

...ring = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> { > def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>; >...

.../nouveau/codegen/nv50_ir_from_tgsi.cpp index 41b91e8..e5b767f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) src0 = fetchSrc(0, c); val0 = getScratch(); mkOp1(OP_FLOOR, TYPE_F32, val0, src0); - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0); } break; case TGSI_OPCOD...

...another roadblock. I attempted what you > suggested and it fixed that issue, but then it started giving a > warning that there is an unknown node in the resulting pattern. > > // unsigned int: f64->i32 ==> f64->f32 + f32->i32 > def : Pat<(i32 (fp_to_uint (f64 GPR:$src0))), > (i32 (fp_to_uint (f32 (dp_to_fp (f64 GPR:$src0)))))>; > 1>Building AMDil.td instruction selector implementation with tblgen > 1>(fp_to_uint:i32 (dp_to_fp:f32 GPR:f64:$src0)) > 1>f:\hq\main\sw\appeng\tools\hpc\llvm\win32\AMDIL\..\bin\Win32\Debug > \TableGe...

...imple. I need to go from 64bit floats to 32bit integers. As the backend doesn't support this natively but has a way of converting it, I'd prefer to get this working via tablegen. What I thought would work from the previous discussion is the following: def : Pat<(fp_to_uint (f64 GPR:$src0)), (fp_to_uint (f32 (dp_to_fp (f64 GPR:$src0))))>; Which when it runs across a 64bit float, it does a double to single conversion, and then calls the 32bit float to int routine. However, tablegen fails with the following error: 1>anonymous.2: (fp_to_uint:isInt GPR:f64:$sr...

Bill, Sorry if I wasn't clear enough. I wasn't referring to multiclass's that define other classes, but with using patterns inside of a multiclass to reduce redundant code. For example: multiclass IntSubtract<SDNode node> { def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1), (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>; } or something similar. I just want to write the pattern once and then have it apply to mul...

Is there currently a way to use a pattern inside of another pattern? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was scrubbed... URL:

...t; index 41b91e8..e5b767f 100644 >> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp >> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) >> src0 = fetchSrc(0, c); >> val0 = getScratch(); >> mkOp1(OP_FLOOR, TYPE_F32, val0, src0); >> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0); >> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0); >> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0...

...floats > to 32bit integers. As the backend doesn’t support this natively but > has a way of converting it, I’d prefer to get this working via > tablegen. > > What I thought would work from the previous discussion is the > following: > def : Pat<(fp_to_uint (f64 GPR:$src0)), > (fp_to_uint (f32 (dp_to_fp (f64 GPR:$src0))))>; > > Which when it runs across a 64bit float, it does a double to single > conversion, and then calls the 32bit float to int routine. > > However, tablegen fails with the following error: > 1>anonymous.2:...

I am attempting to match setcc using tablegen w/ the following patterns: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is there a way around this other than modifying TargetSelectionDAG.td? Also, why is it assumed that all comparison result...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index dfb093c..e38a3b8 100644 ---