search for: sra_part

Displaying 5 results from an estimated 5 matches for "sra_part".

Did you mean: sra_parts
2013 Jan 27
0
[LLVMdev] SHL_PARTS and company
Dear All, I think I understand the motivation for these node types, but I'm not positive: " /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded /// integer shift operations, just like ADD/SUB_PARTS. The operation /// ordering is: /// [Lo,Hi] = op [LoLHS,HiLHS], Amt SHL_PARTS, SRA_PARTS, SRL_PARTS " Okay, for one thing, I can't find a reference to ADD_PARTS...
2014 Oct 03
2
[LLVMdev] Weird problems with cos (was Re: [PATCH v3 2/3] R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO)
...ppen automatically > // during Type Legalization > setOperationAction(ISD::UDIV, MVT::i64, Custom); > @@ -578,6 +585,34 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const > case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG); > case ISD::SRA_PARTS: > case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG); > + case ISD::UADDO: { > + SDLoc DL(Op); > + EVT VT = Op.getValueType(); > + > + SDValue Lo = Op.getOperand(0); > + SDValue Hi = Op.getOperand(1); > + > + SDValue OVF = DAG.getNode(AMDGPUISD::CARRY...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...the result, which is - // still VT. - ExpandOp(Op, Lo, Hi); - break; - } - } - - // If we can emit an efficient shift operation, do so now. - if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) - break; - - // If this target supports SRA_PARTS, use it. - TargetLowering::LegalizeAction Action = - TLI.getOperationAction(ISD::SRA_PARTS, NVT); - if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || - Action == TargetLowering::Custom) { - ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), -...